Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador descarregar pdf (Página 9)

ZestSC1 User Guide

CONFIDENTIAL Page 9 of 57

J4 User I/O Header

IO pins are connected directly to the FPGA. See UCF for FPGA pin connections.

Signal Pin Pin Signal

5V 1 2 3.3V

Ground 3 4 Ground

Ground 5 6 Ground

Ground 7 8 Ground

IO0 9 10 IO1

IO2 11 12 IO3

IO4 13 14 IO5

IO6 15 16 IO7

IO8 17 18 IO9

IO10 19 20 IO11

IO12 21 22 IO13

IO14 23 24 IO15

IO16 25 26 IO17

IO18 27 28 IO19

IO20 29 30 IO21

IO22 31 32 IO23

IO24 33 34 IO25

IO26 35 36 IO27

IO28 37 38 IO29

IO30 39 40 IO31

IO32 41 42 IO33

IO34 43 44 IO35

IO36 45 46 IO37

IO38 47 48 IO39

IO40 49 50 IO41

IO42 51 52 IO43

IO44 53 54 IO45

CLK_IO_P 55 56 CLK_IO_N

IO46 57 58 Ground

Ground 59 60 Ground

Ground 61 62 Ground

Ground 63 64 Ground

J5 2.5 mm power jack for mains adapter

Pin Signal

Centre socket contact - 1 Ground

Switched input pin - 2 VBUS (5V from USB)

Outer socket contact - 3 3.5V to 5.5V POWER IN

When a plug is not inserted, pin 2 VBUS is connected to the jack output pin 3.

When a plug is inserted, the outer contact is isolated from pin 2 and connects the plug

outer contact to the jack output pin 3.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 56 57

Comentários a estes Manuais

Sem comentários

Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador Página 9

Comentários a estes Manuais

Manuais e produtos relacionados com não Cypress Semiconductor NoBL CY7C1472V33