Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador descarregar pdf (Página 22)

Orange Tree Technologies

Page 22 of 57

Figure 8. Approximate Positions of LEDs

7.6 Clocks

The FPGA has two fixed frequency clock inputs of 48MHz each and one clock input from

the IO header. The FPGA’s internal DCM’s can be used to synthesise other clock

frequencies from 1.5MHz to 280MHz.

The 48MHz clock for the Slave FIFO Interface connecting the USB controller and the FPGA

is driven on separate PCB tracks from a crystal oscillator to the USB controller and to the

FPGA. It is connected to FPGA global clock pin GCLK0. It is also used for the FPGA

configuration clock CCLK.

The USB controller 8051 clock is output from the USB controller to the FPGA global clock

pin GCLK1. The frequency can be set to 12MHz, 24MHz or 48MHz by the 8051, and the

8051 firmware supplied with the ZestSC1 sets it to 48MHz. The logic cores supplied with

the board use this USB controller 8051 clock as the main clock. Note this is a separate

clock to the 48MHz GPIF clock described in the paragraph above. The host interface logic

core includes FIFO’s to interface between the two clock domains of the USB controller

8051 clock and the Slave FIFO Interface clock.

The IO clock signals CLK_IO_P and CLK_IO_N are connected to FPGA global clock pins

GCLK6 and GCLK7 respectively. They can be configured as single-ended or differential

clock inputs.

7.7 Power

The board can be either bus-powered or self-powered. Bus-powered means powered

entirely from the USB cable connected to the host computer. If the board is to be bus-

powered then the USB port must be a high power (500mA) port. The DC/DC

converters on the board have been chosen for their very high efficiency of approximately

90%, even at low currents. This is important when the board is bus-powered as only

D3 D4 D5 D9

D8 D7 D6

D10 D11 D13 D12 D1

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 56 57

Sem comentários

Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador Página 22