Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador Página 18

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Orange Tree Technologies
Page 18 of 57
I/O – 49 I/O signals, 2 of which can be a differential pair clock input. The I/O
signals FPGA banks have 51 ohm impedance reference resistors for Spartan DCI
buffers.
There are also 8 LEDs D2-9 that share IO signals 0, 1, & 41-46 respectively. These are
driven active low.
For signal allocations to FPGA pins, see the UCF supplied with the board.
The FPGA is configured from the USB in Slave Parallel mode. Alternatively it can be
configured using JTAG via header J3. The JTAG header on the board is 0.1 inch pitch with
pins assigned to align with the Xilinx Parallel Cable Fly Leads. The download cable should
be the Xilinx Parallel Cable IV with Parallel Cable Flying Leads. Note that the JTAG
reference voltage on pin 1 of J3 is 2.5V.
When using the Xilinx Synthesis Tools XST, the following XST synthesis and
implementation properties should be set.
Synthesis Properties – Xilinx Specific Options
Pack I/O Registers into IOBs YES
Translate Properties
Allow Unmatched LOC Constraints YES
Map Properties
Allow Logic Optimisation Across Hierarchy YES
Perform Timing Driven Packing and Placement YES
Generate Programming File Properties – Configuration Options
Unused IOB Pins Pull Up
Generate Programming File Properties – Startup Options
Drive Done Pin High YES
7.3 Memory
The memory is NoBL (No Bus Latency, the same as ZBT or Zero Bus Turnaround)
pipelined synchronous SRAM from Cypress. The device may be either the 512k x 18 or
4M x 18, according to which was ordered. These devices are respectively the
CY7C1356B-166AC [6] and CY7C1472V33-167AC [7].
The SRAM chip enable pin CE1_n is connected to the FX2 Port E bit 1 so that the FX2 can
control whether the SRAM is enabled to minimise power consumption. The pin CE1_n has
a pull-up so that the SRAM is disabled unless the FX2 enables it by driving this pin low.
MODE, ZZ, CEN_n and CE3_n are all pulled low permanently. CE2 is pulled high
permanently.
All other signals are connected to the FPGA, see the UCF for pin connections. The logic
core supplied with the board includes interface logic for the SRAM. The user interface is
as below.
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