Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador descarregar pdf (Página 15)

ZestSC1 User Guide

CONFIDENTIAL Page 15 of 57

reversing the data flow, select a large value (256 or greater). For applications which

alternate transferring short blocks in either direction, select a short value (such as 16).

User_StreamDataIn is the data stream from the host to the FPGA. The active high

User_StreamDataInWE signal indicates when the data is valid. If the user application

sets User_StreamDataInBusy high then the host will be blocked and no data will be sent

to the user application.

User_StreamDataOut is the data stream from the FPGA to the host. The

User_StreamDataOutWE signal should be set high in the same cycle as the valid data. If

the User_StreamDataOutBusy signal is high then the user application should not attempt

to transfer any more data. The core contains a short FIFO which can accept 4 transfers

after User_StreamDataOutBusy goes high allowing time for the user application to

respond.

Figure 4. Host to FPGA Streaming Cycles

Figure 5. FPGA to Host Streaming Cycles

USER CL

USER StreamDataOut

USER StreamDataOutBus

USER StreamDataOutWE

D2 D1

USER CL

USER StreamDataIn

USER StreamDataInBus

USER StreamDataInWE

D2 D1

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