Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador descarregar pdf (Página 14)

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7.1.1.1 FPGA Configuration

The GPIF mode is used for configuring the FPGA using the SelectMap port. The FX2 acts

as a master driving the FPGA CS_n, WRITE_n and data ports. Data is transferred directly

from the USB port to the GPIF master and on to the FPGA using the Auto Out method

detailed in [3].

7.1.1.2 Streaming Data Transfer

The slave FIFO mode is used to stream data between the host and FPGA. The supplied

FPGA files include a reference design to illustrate use of the slave FIFO interface to

achieve peak transfer rates of 96Mbytes/s and sustained transfer rates only limited by

the host PC. The reference design exposes the following signals:

User_CLK : out std_logic;

User_RST : out std_logic;

User_StreamBusGrantLength : in std_logic_vector(11 downto 0);

User_StreamDataIn : out std_logic_vector(15 downto 0);

User_StreamDataInWE : out std_logic;

User_StreamDataInBusy : in std_logic;

User_StreamDataOut : in std_logic_vector(15 downto 0);

User_StreamDataOutWE : in std_logic;

User_StreamDataOutBusy : out std_logic;

Or, in Verilog:

output User_CLK,

output User_RST,

input [11:0] User_StreamBusGrantLength,

output User_StreamDataIn,

output User_StreamDataInWE,

input User_StreamDataInBusy,

input [15:0] User_StreamDataOut,

input User_StreamDataOutWE,

output User_StreamDataOutBusy,

User_CLK is a clock output from the core. All signals from the core are synchronous to

this clock. All signals to the core should also be synchronous to this clock.

User_RST is an active high global reset output from the core. The user design should

use this to reset its state.

User_StreamBusGrantLength is used by the core to fairly arbitrate between transfers to

and from the host. The bus between the FX and the FPGA is a 16 bit bidirectional

interface and transfers take place in 512 byte blocks (256 sixteen bit words). The FPGA

grants the bus to reads or writes for the number of cycles specified by this input before

reversing the direction. This is done to avoid deadlock where the host wishes to write to

the FPGA and the FPGA wishes to write to the host and to fairly balance reads and writes.

Since a bus turnaround takes a number of cycles, this value is a trade-off between peak

bandwidth (higher with a larger grant length) and turnaround latency (lower with a lower

value). Therefore, for applications which transfer large blocks in one direction before

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