Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador descarregar pdf (Página 41)

ZestSC1 User Guide

CONFIDENTIAL Page 41 of 57

ZestSC1LoadFile

ZESTSC1_STATUS ZestSC1LoadFile( char *FileName,

ZESTSC1_IMAGE *Image);

Parameters

FileName Name of .bit file to use to configure the FPGA.

Image Pointer to location to receive FPGA configuration image.

Return Value

ZESTSC1_SUCCESS Function succeeded

ZESTSC1_NULL_PARAMETER NULL was used illegally as one of the

parameter values

ZESTSC1_FILE_NOT_FOUND File not found

ZESTSC1_FILE_ERROR Error while reading file

ZESTSC1_OUT_OF_MEMORY Not enough memory to complete the

requested operation

ZESTSC1_ILLEGAL_FILE File format is not recognised

ZESTSC1_INVALID_PART_TYPE Illegal FPGA part type

Description

ZestSC1LoadFile can be used to load a .bit file generated by the Xilinx place and route

software into memory for future configuration of the FPGA on the ZestSC1 card. It is

possible to load many configuration files during initialization and select the correct FPGA

image to use during execution of the program. This reduces overhead at configuration

time.

Image is a pointer to a location to receive the configuration image handle. This handle

can be used in future calls to ZestSC1Configure. The handle should be freed by calling

ZestSC1FreeImage when the configuration image is no longer needed.

ZestSC1LoadFile and ZestSC1Configure allow decoupled loading of the bit file and

configuration of the FPGA. Refer to ZestSC1RegisterImage and ZestSC1Configure

for details of how to configure the FPGA from configuration data in memory.

For example:

ZESTSC1_IMAGE Image;

ZESTSC1_HANDLE Handle;

/* Load the .bit file */

ZestSC1LoadImage(“test.bit”, &Image);

/* Other initialization operations here */

/* Open a card with ID of 1 */

ZestSC1OpenCard(1, &Handle);

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Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador Página 41