Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador descarregar pdf (Página 17)

ZestSC1 User Guide

CONFIDENTIAL Page 17 of 57

Figure 6. Register read and write accesses

7.1.1.4 User Signals

The 8 user signals between the FPGA and FX2 can be used for any application defined

purpose. However, care must be taken to set the direction of the FX2 Port C signals such

that the FX2 and FPGA do not drive against each other at any time. Failure to do so may

result in damage to the hardware.

7.1.1.5 Host Interrupt

The user core exposes a single signal to interrupt the host.

User_Interrupt : in std_logic;

Or, in Verilog:

input User_Interrupt

Setting User_Interrupt high for a single cycle will cause an interrupt on the host which

can be trapped by the user application (ZestSC1WaitForInterrupt() function).

7.2 FPGA

The FPGA is from the Xilinx Spartan-3 family and is either the XC3S1000-4 or XC3S400-

4, according to which was ordered. The package is the FT256 256-pin fine pitch thin BGA.

There are three main devices attached to the FPGA:

• USB controller

• SRAM – 512K x 18 or 4M x 18 of synchronous SRAM

USER CL

USER Re

Addr

USER Re

DataIn

USER Re

DataOut

USER Re

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Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador Página 17