Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador descarregar pdf (Página 24)

Orange Tree Technologies

Page 24 of 57

7.8 Build Options

The following modifications can be made to the board by arrangement with Orange Tree

Technologies.

1. DCI reference resistors for the IO lines. DCI buffers require reference

resistors for matching to the characteristic impedance of the IO lines. On ZestSC1

the IO lines are about 50 ohms impedance so the reference resistors are 51

ohms, being the closest standard value. The resistors are connected to the FPGA

pins connected to IO2, 3, 44 & 45, so these IO pins cannot be used if the

reference resistors are fitted. Also LED’s D7 and D8 are connected to IO44 & 45

so these LED’s are removed if the reference resistors are fitted. For the standard

build the reference resistors are not fitted (so DCI cannot be used) and LED’s D7

and D8 are fitted.

2. IO differential clock input. IO pins CLK_IO_P and CLK_IO_N are both

connected to FPGA clock input pins. They can be used either as separate single

ended clocks or general purpose IO or as one differential clock input. A 100 ohm

resistor can be fitted at the FPGA pins to terminate a differential clock input. For

the standard build this resistor is not fitted.

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 56 57

Sem comentários

Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador Página 24