Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador descarregar pdf (Página 16)

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7.1.1.3 Register Reads and Writes

The FX2 external bus is connected to the FPGA allowing memory mapped accesses to

registers implemented inside the FPGA. The supplied FPGA files include a reference

design to illustrate use of registers. The reference design exposes the following signals:

User_CLK : out std_logic;

User_RST : out std_logic;

User_RegAddr : out std_logic_vector(15 downto 0);

User_RegDataIn : out std_logic_vector(7 downto 0);

User_RegDataOut : in std_logic_vector(7 downto 0);

User_RegWE : out std_logic;

User_RegRE : out std_logic;

Or, in Verilog:

output User_CLK,

output User_RST,

output [15:0] User_RegAddr,

output [7:0] User_RegDataIn,

input [7:0] User_RegDataOut,

output User_RegWE,

output User_RegRE

User_CLK is a clock output from the core. All signals from the core are synchronous to

this clock. All signals to the core should also be synchronous to this clock.

User_RST is an active high global reset output from the core. The user design should

use this to reset its state.

User_RegAddr is the zero based address of the read or write access. Note that registers

between 0x0000 and 0x2000 are not available on boards fitted with the Cypress FX2LP

USB controller (part number CY68013A).

User_RegDataIn is the data from the host to the FPGA during a register write.

User_RegDataOut is the data from the FPGA to the host during a register read.

User_RegWE is an active high write strobe. This strobe will be high for a single cycle

simultaneously with the address and data.

User_RegRE is an active high read strobe. The user application should return the data on

the rising edge of the clock when this strobe is high.

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Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador Página 16