Cypress Semiconductor NoBL CY7C1472V33 Guia do Utilizador descarregar pdf (Página 53)

ZestSC1 User Guide

CONFIDENTIAL Page 53 of 57

/* Configure the FPGA */

ZestSC1ConfigureFromFile(Handle, “example.bit”);

/* Set the signal to ‘active’ */

ZestSC1SetSignals(Handle, 1);

/* Set the signal to ‘inactive’ */

ZestSC1SetSignals(Handle, 0);

/* Close the card */

ZestSC1CloseCard(Handle);

Driving a signal from both the host and FPGA may damage

the ZestSC1 hardware.

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