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36-Mbit QDR

II SRAM 2-Word

Burst Architecture

CY7C1412BV18

CY7C1414BV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-07036 Rev. *E Revised August 24, 2009

Features

■ Separate independent Read and Write Data Ports

❐ Supports concurrent transactions

■ 250 MHz clock for high bandwidth

■ 2-word burst on all accesses

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 500 MHz) at 250 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR

II operates with 1.5 cycle read latency when Delay Lock

Loop (DLL) is enabled

■ Operates as a QDR I device with 1 cycle read latency in DLL

off mode

■ Available in x 18, and x 36 configurations

■ Full data coherency, providing most current data

■ Core V

= 1.8V (±0.1V); I/O V

DDQ

= 1.4V to V

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1412BV18 – 2M x 18

CY7C1414BV18 – 1M x 36

Functional Description

The CY7C1412BV18, and CY7C1414BV18 are 1.8V

Synchronous Pipelined SRAMs, equipped with QDR II archi-

tecture. QDR II architecture consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. QDR II

architecture has separate data inputs and data outputs to

completely eliminate the need to ‘turnaround’ the data bus

required with common I/O devices. Access to each port is

accomplished through a common address bus. The read

address is latched on the rising edge of the K clock and the write

address is latched on the rising edge of the K

clock. Accesses to

the QDR II read and write ports are completely independent of

one another. To maximize data throughput, both read and write

ports are provided with DDR interfaces. Each address location

is associated with two 18-bit words (CY7C1412BV18), or 36-bit

words (CY7C1414BV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K

and C

and C), memory bandwidth is maximized while simplifying

system design by eliminating bus ‘turnarounds’.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 250 200 167 MHz

Maximum Operating Current x18 850 725 650 mA

x36 1000 850 740

[+] Feedback

1 2 3 4 5 6 ... 23 24

Resumo do Conteúdo

Página 1 - Burst Architecture

36-Mbit QDR® II SRAM 2-WordBurst ArchitectureCY7C1412BV18CY7C1414BV18Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709

Página 2

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 10 of 24IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs incorporate a serial boundary sc

Página 3

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 11 of 24IDCODEThe IDCODE instruction loads a vendor-specific, 32-bit code intothe instructi

Página 4

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 12 of 24TAP Controller State DiagramThe state diagram for the TAP controller follows.[9]TES

Página 5

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 13 of 24TAP Controller Block DiagramTAP Electrical Characteristics Over the Operating Range

Página 6

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 14 of 24TAP AC Switching Characteristics Over the Operating Range[13, 14]Parameter Descript

Página 7

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 15 of 24Identification Register Definitions Instruction FieldValueDescriptionCY7C1412BV18 C

Página 8

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 16 of 24Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID0 6R 28

Página 9

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 17 of 24Power Up Sequence in QDR II SRAMQDR II SRAMs must be powered up and initialized in

Página 10 - CY7C1414BV18

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 18 of 24Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. T

Página 11

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 19 of 24ISB1Automatic Power down CurrentMax VDD, Both Ports Deselected, VIN ≥ VIH or VIN ≤

Página 12

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 2 of 24Logic Block Diagram (CY7C1412BV18)Logic Block Diagram (CY7C1414BV18)1M x 18 ArrayCLK

Página 13

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 20 of 24Switching Characteristics Over the Operating Range[20, 21]CypressParameterConsortiu

Página 14

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 21 of 24Switching WaveformsFigure 5. Read/Write/Deselect Sequence[26, 27, 28]K1234581067KR

Página 15

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 22 of 24Ordering InformationThe table below contains only the parts that are currently avai

Página 16

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 23 of 24Package DiagramFigure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85195A1PIN 1 CORNER17

Página 17

Document #: 001-07036 Rev. *E Revised August 24, 2009 Page 24 of 24QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cyp

Página 18

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 3 of 24Pin Configuration The pin configuration for CY7C1412BV18 and CY7C1414BV18 follow.[1]

Página 19

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 4 of 24Pin Definitions Pin Name I/O Pin DescriptionD[x:0]Input-SynchronousData Input Signal

Página 20

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 5 of 24DOFFInput DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL

Página 21

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 6 of 24Functional OverviewThe CY7C1412BV18, and CY7C1414BV18 are synchronouspipelined Burst

Página 22

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 7 of 24Programmable ImpedanceAn external resistor, RQ, must be connected between the ZQ pin

Página 23

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 8 of 24Truth TableThe truth table for CY7C1412BV18, and CY7C1414BV18 follows.[2, 3, 4, 5, 6

Página 24

CY7C1412BV18CY7C1414BV18Document #: 001-07036 Rev. *E Page 9 of 24Write Cycle DescriptionsThe write cycle description table for CY7C1414BV18 follows.[

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