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the data by 2 further clocks as required by the ZBT SRAM. Byte write strobes are not

implemented.

For read cycles the user logic drives the read strobe high and the read address in the

same clock cycle, and the logic core registers all these signals. Valid data is returned to

the user code 4 clocks after the user code drives the read strobe high. The valid data is

accompanied by the active high data valid strobe. When the data valid strobe is high then

the read data should be registered by the user code.

All accesses are single accesses requiring a valid address with each access, burst

accesses are not implemented. There is no difference in bandwidth between single and

burst accesses.

The SRAM clock is driven from the FPGA to the SRAM. This must arrive at the SRAM

before the command and write data by the SRAM hold time of at least 0.5nS. This is

achieved by using a DCM to generate an SRAM clock about 2nS in advance of the User

clock and clocking all signals in IOB's. The SRAM clock is used only as an output to the

SRAM (via FDDR in IOB) and does not clock any signals in the FPGA.

The data tri-state signal flip-flop is placed in each data IOB to minimize bus contention

when changing from write to read or vice versa (see next paragraph). This is achieved by

setting the Synthesis property “Pack I/O Registers into IOBs” to YES.

ZBT Zero Bus Turnaround means that there does not have to be an idle cycle between

different types of cycles (i.e. writes and reads). The direction of the data bus therefore

needs to be able to change just after the start of a clock cycle from one device (e.g.

SRAM) driving it to the other device (e.g. FPGA) driving it. Because of differences in turn

on and turn off times of the different devices' data bus drivers there will inevitably be

some bus contention. However, as [8] shows, bus contention of a few nS is easily

tolerable.

7.4 IO

J4 provides user I/O from the FPGA, see the Headers section for the names of signals

connected to the pins and the UCF for connections to the FPGA. J4 is a 32 pins x 2 rows

0.1 inch pitch header.

49 pins are connected directly to the FPGA for user I/O. Two of these signals (CLK_IO_P

and CLK_IO_N) are connected to clock input pins on the FPGA. They can have a 100 ohm

parallel termination resistor across them at the FPGA for a differential clock – see section

Build Options. Also signals IO2-45 may be used as differential pairs IO2 & 3, IO4 & 5, …,

IO44 & 45, but they do not have termination resistors on the board.

IO0, 1, 41-46 are also connected to LED’s D2 to D9 respectively – see section LED’s. An

LED is switched on when the IO line is low, and requires 2mA to be drawn by the IO line

for full brightness.

There are 6 ground pins at one end of J4 and 7 ground pins at the other end. Pin 1 is 5V

power output and pin 2 is 3.3V power output, both via resettable 1.5A fuses. This power

can be used for example to power a daughter card plugged onto J4. The 3V3 is from the

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