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Chapter 1. Introducing EZ-USB FX2 Page 1-25

1.19 External FIFO Interface

The large data FIFOs (endpoints 2, 4, 6 and 8) in the FX2 are designed to move high speed (480

Mbits/sec) USB data on and off chip without introducing any bandwidth bottlenecks. They accom-

plish this goal by implementing the following features:

1. Direct interface with outside logic, with the FX2’s CPU out of the data path.

2. “Quantum FIFO” architecture instantaneously moves (“commits”) packets between the USB

and the FIFOs.

3. Versatile interfaces: Slave FIFO (external master) or GPIF (internal master), synchronous or

asynchronous clocking, internal or external clocks, etc.

The firmware sets switches to configure the outside FIFO interface, and then generally does not

participate in moving the data into and out of the FIFOs.

To understand the “Quantum FIFO”, it is necessary to refer to two data domains, the

USB domain

and the

Interface domain

. Each domain is independent, allowing different clocks and logic to han-

dle its data.

The USB domain is serviced by the SIE, which receives and delivers FIFO data packets over the

two-wire USB bus. The USB domain is clocked using a reference derived from the 24 MHz crystal

attached to the FX2 chip.

The Interface domain loads and unloads the endpoint FIFOs. An external device such as a DSP or

ASIC can supply its own clock to the FIFO interface, or the FX2’s internal interface clock (IFCLK)

can be supplied to the interface.

The classic solution to the problem of reconciling two different and independent clocks is to use a

FIFO. The FX2’s FIFOs have an unusual property: They’re

Quantum

FIFOs, which means that

data is committed to the FIFOs in USB-size packets, rather than one byte at a time. This is invisible

to the outside interface, since it services the FIFOs just like any ordinary FIFO (i.e., by checking full

and empty flags). The only minor difference is that when an empty flag goes from 1 (empty) to 0

(not empty), the number of bytes in the FIFO jumps to a USB packet size, rather than just one

byte.

FX2 Quantum FIFOs may be moved between data domains almost instantaneously. The Quantum

nature of the FIFOs also simplifies error recovery. If endpoint data were continuously clocked into

an interface FIFO, some of the packet data might have already been clocked out by the time an

error is detected at the end of a USB packet. By switching FIFO data between the domains in

USB-packet-size blocks, each USB packet can be error-checked (and retried, if necessary) before

it’s committed to the other domain.

Figures 1-16 and 1-17 illustrate the two methods by which external logic interfaces to the endpoint

FIFOs EP2, EP4, EP6 and EP8.

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Cypress Semiconductor FX2LP Informações Técnicas Página 51