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EZ-USB FX2 Technical Reference Manual

Page 10-10 EZ-USB FX2 Technical Reference Manual v2.1

10.2.10 Connecting GPIF Signal Pins to Hardware

The first step in creating the interface between the FX2’s GPIF and an external peripheral is to

define the hardware interconnects.

1. Choose IFCLK settings. Decide whether to use an asynchronous or synchronous interface.

If synchronous, choose either the internal or external interface clock. If internal, choose either

30 or 48 MHz; if external, ensure that the frequency of the external clock is in the range 5-48

MHz.

2. Determine the proper FIFO Data Bus size. If the data bus for the interface is 8 bits wide, use

the FD[7:0] pins and set WORDWIDE=0. If the data bus for the interface is 16 bits wide, use

FD[15:0] and set WORDWIDE=1.

3. Assign the CTLx signals to the interface. Make a list of all interface signals to be driven

from the GPIF to the peripheral, and assign them to the CTL[5:0] inputs. If there are more out-

put signals than available CTL outputs, non-GPIF I/O signals must be driven manually by FX2

firmware. In this case, the CTLx outputs should be assigned only to signals that must be

driven as part of a data transaction.

4. Assign the RDYn signals to the interface. Make a list of all interface signals to be driven

from the peripheral to the GPIF, and assign them to the RDY[5:0] inputs. If there are more

input signals than available RDY inputs, non-GPIF I/O signals must be sampled manually by

FX2 firmware. In this case, the RDYn inputs should be used only for signals that must be sam-

pled as part of a data transaction.

5. Determine the proper GPIF Address connections. If the interface uses an Address Bus,

use the GPIFADR[8:0] signals for the least significant bits, and other non-GPIF I/O signals for

the most significant bits. If the address pins are not needed (as when, for instance, the periph-

eral is a FIFO) they may be left unconnected.

10.2.11 Example GPIF Hardware Interconnect

The following example illustrates the hardware connections that can be made for a standard inter-

face to a 27C256 EPROM.

The process is the same for larger, more-complicated interfaces.

Table 10-4. Example GPIF Hardware Interconnect

Step Result Connection Made

1. Choose IFCLK settings. Internal IFCLK, 48MHz, Async, GPIF. No connection.

2. Determine proper FIFO

Data Bus size.

8 bits from the EPROM. FD[7:0] to D[7:0]. Firmware

writes WORDWIDE=0.

3. Assign CTLx signals to

the interface.

and OE are inputs to the EPROM. CTL0 to CS.

CTL1 to OE

4. Assign RDYn signals to

the interface.

27C256 EPROM has no

output ready/wait signals.

No connection.

5. Determine the proper

GPIFADR connections.

16 bits of address. GPIFADR[8:0] to A[8:0] and

other I/O pins to A[15:9].

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