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manuais Cypress Semiconductor FX2LP

Manuais de instruções e guias do utilizador para Redes Cypress Semiconductor FX2LP.
Disponibilizamos 6 manuais Cypress Semiconductor FX2LP em pdf para descarga gratuita: Manual do Utilizador, Informações Técnicas, Guia de Instalação, Ficha Técnica, Especificações


Cypress semiconductor FX2LP Manual do Utilizador (60 páginas)


Marca: Cypress-semiconductor | Categoria: Redes | Tamanho: 3.16 MB |

 

Índice

CY7C68013A/CY7C68014A

1

CY7C68015A/CY7C68016A

1

3.5 USB Boot Methods

4

3.6 ReNumeration™

4

3.7 Bus-powered Applications

4

3.8 Interrupt System

4

Inside FX2LP Outside FX2LP

8

3.11 Register Addresses

9

3.12 Endpoint RAM

9

Port GPIF Master Slave FIFO

15

128-pin TQFP

16

100-pin TQFP

17

56-pin SSOP

18

5.0 Register Summary

29

R = all bits read-only

35

W = all bits write-only

35

10.2 Program Memory Read

38

10.3 Data Memory Read

39

10.4 Data Memory Write

40

10.6 GPIF Synchronous Signals

42

10.17 Sequence Diagram

50

12.0 Package Diagrams

55

Package Diagrams

55

51-85050-*B

56

51-85101-*C

57

A1 CORNER

58

PCB Material

59

Cypress semiconductor FX2LP Informações Técnicas (460 páginas)


Marca: Cypress-semiconductor | Categoria: Redes | Tamanho: 2.87 MB |

 

Índice

EZ-USB FX2

1

Technical Reference

1

Cypress Disclaimer Agreement

2

List of Trademarks

2

Table of Contents

3

Chapter 4. Interrupts

4

Chapter 5. Memory

5

Chapter 6. Power Management

5

Chapter 7. Resets

5

Chapter 9. Slave FIFOs

6

Chapter 11. CPU Introduction

8

Chapter 12. Instruction Set

9

Chapter 13. Input/Output

9

(Table of Contents)

10

Chapter 15. Registers

10

Appendix A

12

Appendix B

12

Appendix C

12

List of Figures

13

(List of Figures)

14

List of Tables

21

(List of Tables)

22

1.1 Introduction

27

1.2 An Introduction to USB

27

1.3 The USB Specification

28

1.4 Host Is Master

29

1.5 USB Direction

29

1.6 Tokens and PIDs

29

1.7 USB Frames

31

1.8 USB Transfer Types

32

1.8.3 Isochronous Transfers

33

1.8.4 Control Transfers

33

1.9 Enumeration

34

Interface

35

1.11 ReNumeration™

36

1.13 FX2 Feature Summary

39

1.15 FX2 Block Diagram

41

1.16 Packages

42

1.16.2 100-Pin Package

43

1.16.3 128-Pin Package

43

GPIF Master

45

Slave FIFO

45

CY7C68013

46

128-pin TQFP

46

100-pin TQFP

47

56-pin SSOP

48

1.18 FX2 Endpoint Buffers

49

Characteristic Choices

50

Direction IN, OUT

50

1.19 External FIFO Interface

51

FD[15:0]

53

Chapter 2 Endpoint Zero

55

2.2 Control Endpoint EP0

56

SETUP Stage

57

SETUPDAT

57

Initialization

58

Data transfer

58

Interrupt Control

58

DAT. The Field column

59

2.3.2 Set Feature

64

2.3.3 Clear Feature

65

2.3.4 Get Descriptor

66

DATA Stage

67

STATUS Stage

67

2.3.5 Set Descriptor

71

2.3.5.1 Set Configuration

74

2.3.6 Get Configuration

74

2.3.7 Set Interface

75

2.3.8 Get Interface

76

2.3.9 Set Address

76

2.3.10 Sync Frame

77

2.3.11 Firmware Load

78

3.1 Introduction

79

3.2 FX2 Startup Modes

79

3.3 The Default USB Device

81

USB Disconnect

86

I²C-compatible bus speed

86

3.6 The RENUM Bit

87

3.10 Multiple ReNumerations™

90

Chapter 4 Interrupts

91

4.2 SFRs

92

4.3 Interrupt Processing

96

4.3.1.1 Interrupt Priorities

97

4.4 USB-Specific Interrupts

98

4.4.2 USB Interrupts

99

USB Interrupt

100

Interrupt

102

4.4.2.2 SOF Interrupt

103

4.4.2.3 Suspend Interrupt

103

4.4.2.4 USB RESET Interrupt

103

4.4.2.5 HISPEED Interrupt

103

4.4.2.6 EP0ACK Interrupt

103

4.4.2.7 Endpoint Interrupts

104

4.4.2.9 EPxPING Interrupt

104

4.4.2.10 ERRLIMIT Interrupt

105

4.4.2.11 EPxISOERR Interrupt

105

Instruction

106

D7 D6 D5 D4 D3 D2 D1 D0

108

Address Op-Code Hex Value

110

0x0053 LJMP 0x02

110

0x0054 AddrH 0xHH

110

0x0055 AddrL 0xLL

110

Chapter 5 Memory

113

5.2.1 The Lower 128

114

5.2.2 The Upper 128

114

Standard 8051

115

5.3.1 56- and 100-pin FX2

116

5.3.2 128-pin FX2

116

5.4 FX2 Memory Maps

117

Inside FX2 Outside FX2

119

Chapter 5. Memory Page 5-9

121

Chapter 6 Power Management

123

USB RESUME

124

WAKEUP pin

124

6.2 USB Suspend

125

6.3 Wakeup/Resume

126

6.3.1 Wakeup Interrupt

127

6.4.1 WU2 Pin

128

Chapter 7 Resets

131

7.2 Power-On Reset (POR)

132

7.3 Releasing the CPU Reset

133

7.4 CPU Reset Effects

134

7.5 USB Bus Reset

134

7.6 FX2 Disconnect

135

7.7 Reset Summary

135

8.1 Introduction

137

8.6.1.1 EP0CS

141

8.6.1.2 EP0BCH and EP0BCL

143

8.6.1.3 USBIE, USBIRQ

143

8.6.1.4 EP01STAT

144

8.6.1.5 EP1OUTCS

144

8.6.1.6 EP1OUTBC

145

8.6.1.7 EP1INCS

145

8.6.1.8 EP1INBC

145

8.6.2.1 EP2468STAT

146

0 0 Invalid

147

8.6.3.2 EPIE, EPIRQ

151

8.6.3.4 TOGCTL

152

8.7 The Setup Data Pointer

153

0xE6B3 SUDPTRH High address

154

0xE6B4 SUDPTRL Low address

154

0xE6B5 SUDPTRCTL SDPAUTO bit

154

8.8 Autopointers

155

Chapter 9 Slave FIFOs

157

9.2 Hardware

158

FIFOADR[1:0]:

164

Read — SLOE and SLRD:

164

Write — SLWR:

164

PKTEND:

165

9.3 Firmware

175

9.3.2 EPx Memories

176

AUTOOUT=1

178

10.1 Introduction

191

10.2 Hardware

195

10.2.4 Six Ready IN signals

197

10.3.1 The GPIF Registers

202

10.3.2.1 The GPIF IDLE State

202

10.3.2.2 Defining States

204

10.3.4 State Instructions

211

10.4 Firmware

216

10.4.3.1 Transaction Counter

231

10.4.4 GPIF Flag Selection

232

10.4.5 GPIF Flag Stop

232

10.5 UDMA Interface

253

Chapter 11 CPU Introduction

255

11.2 8051 Enhancements

256

11.3 Performance Overview

257

11.4 Software Compatibility

258

11.6 FX2/DS80C320 Differences

259

11.6.4 Watchdog Timer

260

11.6.5 Power Fail Detection

260

11.6.6 Port I/O

260

11.6.7 Interrupts

260

11.8 EZ-USB FX2 Internal RAM

261

11.9 I/O Ports

262

11.10Interrupts

263

11.11 Power Control

263

11.14Reset

265

Chapter 12 Instruction Set

267

12.1.1 Instruction Timing

271

12.1.3 Dual Data Pointers

273

Table 12-2

274

Chapter 13 Input/Output

275

IOE Port E SFR 0xB1

278

PORTCCFG

283

(0xE671)

283

Bits")

286

13.4.2 Registers

287

0 0 0 0 0 0 STOPE 400KHZ

288

13.4.2.2 Status Bits

289

ID1, ID0

290

13.4.3 Sending Data

290

13.4.4 Receiving Data

290

13.5 EEPROM Boot Loader

291

0 0 No EEPROM detected

292

1 1 Not used

292

14.1 Introduction

293

14.2 Timers/Counters

293

14.2.2 Timers 0 and 1

294

14.2.3 Timer Rate Control

299

14.2.4 Timer 2

300

14.3 Serial Interface

304

14.3.3 Mode 0

307

D0 D1 D2 D3 D4 D5 D6 D7

310

D1 D2 D3 D4 D5 D6 D7

310

14.3.4 Mode 1

312

14.3.4.1 Mode 1 Baud Rate

312

14.3.4.2 Mode 1 Transmit

314

14.3.5 Mode 1 Receive

314

14.3.6 Mode 2

316

14.3.6.1 Mode 2 Transmit

316

14.3.6.2 Mode 2 Receive

317

14.3.7 Mode 3

318

Chapter 15 Registers

321

15.1.2 Other Conventions

322

15.3 About SFRS

324

R R R R R R R R

327

0 1 0 1 1 0 1 0

327

SFR 0xBF

332

and WR strobes

333

Bit 1 CLKOE Drive CLKOUT Pin

334

0 30 MHz

335

1 48 MHz(default)

335

Bit 3-0 EP3:0 Endpoint

340

Bit 3 Break Enable Breakpoint

340

Bit 1 BPEN Breakpoint Enable

341

Bit 5 PKTEND

342

Bit 3 SLRD FIFO Read Polarity

343

Bit 1 EF Empty Flag Polarity

343

Bit 0 FF Full Flag Polarity

343

15.5.9 Chip Revision Control

344

Chip Revision Control E60B

344

15.5.10 GPIF Hold Time

345

GPIFHOLDTIME E60C

345

15.6 Endpoint Configuration

346

VALID DIR TYPE1 TYPE0 0 0 0 0

347

Bit 6 INFM1 IN Full Minus One

349

Bit 5 OEP1 OUT Empty Plus One

349

0 0 0 0 0 0 0 0

352

Bit 1-0 PFC9:8 PF Threshold

355

Bit 7 DECIS PF Polarity

357

Bit 6 PKSTAT Packet Status

357

Bit 0 PFC8 PF Threshold

357

Bit 7-0 PFC7:0 PF Threshold

358

15.6.5.1 IN Endpoints

359

15.6.5.2 OUT Endpoints

360

Bit 7 SKIP Skip Packet

362

Bit 3-0 EP3:0 Endpoint Number

362

Bit 2 PF Programmable Flag

363

Bit 1 EF Empty Flag

364

Bit 0 FF Full Flag

364

EP8 EP6 EP4 EP2 EP1 EP0 0 IBN

366

0 0 0 0 0 0 GPIFWF GPIFDONE

370

Bit 0 ERRLIMIT Error Limit

371

Bit 7-4 EC3:0 USB Error Count

372

1 0 I4V3 I4V2 I4V1 I4V0 0 0

373

Bit 1 INT4SRC INT 4 Source

374

Bit 6 SLCS SLCS

375

Alternate Configuration

375

Bit 6 T2EX Timer 2 Counter

376

I2CS I²C-Compatible Bus

377

Control and Status

377

Bit 5 LASTRD Last Data Read

378

Bit 4-3 ID1:0 Boot EEPROM ID

378

Bit 2 BERR Bus Error

378

Bit 1 ACK Acknowledge Bit

378

Bit 0 DONE Transfer DONE

378

Bit 7-0 Data Data Bits

379

Bit 7-0 Data AUTODATAx

380

15.9 UDMA CRC Registers

381

Bit 7 QENABLE

382

Bit 3 QSTATE

382

Bits 2-0 QSIGNAL[2:0]

382

Bit 7 HSM High Speed Mode

383

Bit 1 RENUM Renumerate

383

Regardless of Bus State

384

15.10.4 Data Toggle Control

385

Bit 3-0 EP3:0 Select Endpoint

386

15.10.6 USB Frame Count Low

387

15.10.7 USB Microframe Count

387

15.11 Endpoints

388

0 BC6 BC5 BC4 BC3 BC2 BC1 BC0

389

Bit 7-0 BC7:0 Byte Count

391

Bit 7 HSNAK Hand Shake w/ NAK

391

Bit 1 BUSY EP0 Buffer Busy

392

Bit 0 STALL EP0 Stalled

392

Bit 3 FULL Endpoint FIFO Full

394

Bit 0 STALL ENDPOINT STALL

394

R R R R R R R R/W

395

0 0 0 0 0 1 0 0

395

Bit 7-0 BC7:0 Byte Count High

399

Bit 15-0 A15:0

400

0 0 0 0 0 0 0 SDPAUTO

401

DONE 0 0 0 0 0 0 IDLEDRV

403

15.12.3 CTL Outputs

404

0 1 Open-Drain Open-Drain

405

15.12.4 GPIF Address High

406

GPIFADRH

406

GPIF Address High E6C4

406

15.12.5 GPIF Address Low

407

GPIFADRL

407

GPIF Address Low E6C5

407

FLOWSTATE E6C6

407

FLOWLOGIC E6C7

408

Bits 2-0 TERMB[2:0]

409

Bit 7 SLAVE

411

Bit 6 RDYASYNC

412

Bit 5 CTLTOGL

412

Bit 4 SUSTAIN

412

Bit 2-0 MSTB[2:0]

412

Bits 7-4 HOPERIOD[3:0]

413

Bit 3 HOSTATE

413

Bits 2-0 HOCTL[2:0]

413

Bit 1 FALLING

413

Bit 0 RISING

413

FLOWSTBHPERIOD E6CD

414

GPIFTCB3

415

GPIFTCB2

415

GPIFTCB1

416

GPIFTCB0

416

FS1 FS0 Flag

417

Bit 7-0 D15:8 GPIF Data High

419

INTRDY SAS TCXRDY5 0 0 0 0 0

420

15.12.15 GPIF RDY Pin Status

421

15.12.16 Abort GPIF Cycles

421

GPIFABORT Abort GPIF E6F5

421

Bit 7-0 D7:0 EP0 Data

422

Bit 7-0 D7:0 EP1-Out Data

422

Bit 7-0 D7:0 EP1-IN Buffer

423

Bit 7-0 D7:0 EP2 Data

423

Bit 7-0 D7:0 EP4 Data

424

Bit 7-0 D7:0 EP6 Data

424

Bit 7-0 D7:0 EP8 Data

425

n means “round n upward”

426

Table A-2 Device Qualifier

428

Field Description Value

428

Register Summary

449

Cypress semiconductor FX2LP Guia de Instalação (28 páginas)


Marca: Cypress-semiconductor | Categoria: Redes | Tamanho: 0.57 MB |

 

Índice

Getting Started

1

Development Kit Manual

1

Cypress Disclaimer Agreement

2

Table of Contents

3

1.2.2 Other Suggested Tools

6

2.1 System Requirements

6

3.0 Installing the Hardware

8

4.1 Introduction

10

4.2 Schematic Summary

10

4.3 Jumpers

11

“Small” 16x8 000 24LC00

12

128x8 000 24LC01

12

256x8 000 24LC02

12

“Large” 8Kx8 001 24LC64/5

12

4.5 Interface Connectors

13

4.6 ATA Connector P8

16

4.7 U2 -- 22v10 GAL

17

4.8 Memory Maps

17

C Expanders

18

CY7C68013A-128AZC

27

Cypress semiconductor FX2LP Ficha Técnica (13 páginas)


Marca: Cypress-semiconductor | Categoria: Redes | Tamanho: 0.22 MB |

 

Índice

AN76348

1

Migrating from EZ-USB

1

Introduction

2

Architectural Differences

2

Serial Interfaces

2

GPIF versus GPIF II

2

Booting Options

3

Crystal / Clock

3

Decoupling Capacitance

3

BulkLoop Example on FX2LP

4

Programmer’s View of FX3

5

FX3 Firmware Stack

6

BulkLoop Example on FX3

6

Tool Chain Initialization

7

Device Initialization

7

Application Definition

8

Application Code

8

Application Thread

9

Debug Initialization

9

Application Initialization

10

Available Collateral

11

About the Author

11

Document History

12

Products

13

Solutions

13

Cypress semiconductor FX2LP Especificações (10 páginas)


Marca: Cypress-semiconductor | Categoria: Redes | Tamanho: 0.31 MB |

 

Índice

Migrating From EZ-USB

1

FX2™ to EZ-USB FX2LP™

1

Migrating from FX2 to FX2LP

2

Details of Firmware Changes

4

Feature Enhancements

6

EZ-USB FX2LP Whole Product

7

Support Collateral

7

Summary

8

About the Author

8

Document History

9

Cypress semiconductor FX2LP Ficha Técnica (66 páginas)


Marca: Cypress-semiconductor | Categoria: Redes | Tamanho: 0.88 MB |

 

Índice

FX2LP™ USB Microcontroller

1

Data (8)

2

CY7C68013A, CY7C68014A

10

CY7C68015A, CY7C68016A

10

0.017” dia

62

Solder Mask

62

Cu Fill

62

0.013” dia

62




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