Cypress Semiconductor FX2LP Informações Técnicas descarregar pdf (Página 334)

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EZ-USB FX2 Technical Reference Manual

Page 15-14 EZ-USB FX2 Technical Reference Manual v2.1

The RD and WR strobes are asserted for two CLKOUT cycles; the WR strobe asserts two

CLKOUT cycles after the PORTC pins are updated.

If a design uses the 128-pin FX2 and connects off-chip memory to the address and data

buses, this bit should be set to zero. This is because the RD

and WR pins are also the stan-

dard strobes used to read and write off-chip memory, so normal reads/writes to I/O Port C

would disrupt normal accesses to that memory.

Bit 4-3 CLKSPD1:0 CPU Clock Speed

These bits set the CPU clock speed. At power-on-reset, these bits default to 00 (12 MHz).

Firmware may modify these bits at any time.

Bit 2 CLKINV Invert CLKOUT Signal

CLKINV=0: CLKOUT signal not inverted (as shown in all timing diagrams).

CLKINV=1: CLKOUT signal inverted.

Bit 1 CLKOE Drive CLKOUT Pin

CLKOE=1: CLKOUT pin driven.

CLKOE=0: CLKOUT pin floats.

15.5.2 Interface Configuration (Ports, GPIF, slave FIFOs)

Figure 15-8. Interface Configuration (Ports, GPIF, slave FIFOs)

Table 15-4. CPU Clock Speeds

CLKSPD1 CLKSPD0 CPU Clock

0 0 12 MHz (Default)

0 1 24 MHz

1 0 48 MHz

1 1 Reserved

IFCONFIG Interface Configuration(Ports, GPIF,

slave FIFOs)

E601

b7 b6 b5 b4 b3 b2 b1 b0

IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0

R/W R/W R/W R/W R/W R/W R/W R/W

1 1 0 0 0 0 0 0

1 2 ... 329 330 331 332 333 334 335 336 337 338 339 ... 459 460

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