Cypress Semiconductor FX2LP Informações Técnicas descarregar pdf (Página 369)

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Chapter 15. Registers Page 15-49

15.7.5 Endpoint Interrupt Enable/Request

Figure 15-45. Endpoint Interrupt Enables

Figure 15-46. Endpoint Interrupt Requests

These Endpoint interrupt enable/request registers indicate the pending interrupts for each bulk

endpoint. For IN endpoints, the interrupt asserts when the host takes a packet from the endpoint;

for OUT endpoints, the interrupt asserts when the host supplies a packet to the endpoint.

The IRQ bits function independently of the Interrupt Enable (IE) bits, so interrupt requests are held

whether or not the interrupts are enabled.

Do not clear an IRQ bit by reading an IRQ Register, ORing its contents with a bit mask, and writing

back the IRQ Register. This will clear ALL pending interrupts. Instead, simply write the bit mask

value (with a “1” in the bit position of the IRQ you want to clear) directly to the IRQ Register.

EPIE Endpoint Interrupt Enables (INT2) E65E

b7 b6 b5 b4 b3 b2 b1 b0

EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN

R/W R/W R/W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0 0

EPIRQ Endpoint Interrupt Requests (INT2) E65F

b7 b6 b5 b4 b3 b2 b1 b0

EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN

R/W R/W R/W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0 0

1 2 ... 364 365 366 367 368 369 370 371 372 373 374 ... 459 460

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