
Chapter 15. Registers Page 15-35
By default, FLAGA is the Programmable-Level Flag (PF) for the endpoint currently pointed to by
the FIFOADR[1:0] pins. For EP2 and EP4, the default endpoint configuration is BULK, OUT, 512,
2x, and the PF pin asserts when the entire FIFO has greater than/equal to 512 bytes. For EP6 and
EP8, the default endpoint configuration is BULK, IN, 512, 2x, and the PF pin asserts when the
entire FIFO has less than/equal to 512 bytes.
In other words, the default-configuration PFs for EP2 and EP4 assert when the FIFOs are half-full,
and the default-configuration PFs for EP6 and EP8 assert when those FIFOs are half-empty.
In the first example below, bits 5-3 have data that is required to complete the transfer. In the sec-
ond example, bits 5-3 do not matter - those bits are don’t cares because PKTSTAT=1:
Example 1:
Assume a Bulk IN transfer over Endpoint 2 and PKTSTAT=0:
EP2FIFOPFH = 0001 0000
• b6=0 (or PKTSTAT=0): this indicates that the transfer will include packets (as defined
by bits 5, 4, and 3) plus bytes (the sum in the flag low register)
• b5b4b3=010 binary (or 2 decimal): this indicates the number of packets to expect dur-
ing the transfer (in this case, two packets…)
EP2FIFOPFL = 0011 0010
•…plus 50 bytes in the currently filling packet
(the sum of the binary bits in the EP2FIFOPFL register is 2 +16 + 32 = 50 decimal)
DECIS=0, thus PF activates when less than 2 PKTS+50 bytes.
Example 2:
To perform an IN transfer of a number over the same endpoint, set PKTSTAT=1 and write a value
into the EP2FIFOPFL register:
EP2FIFOPFH = 01xxx000
EP2FIFOPFL = 75
Setting PKTSTAT=1 causes the PF decision to be based on the byte count alone, ignoring the
packet count. This mode is valuable for double-buffered endpoints, where only the byte count of
the currently-filling packet is important.
DECIS=0, thus PF activates when less than 75 bytes in the current PKTS.
Bit 1-0 PFC9:8 PF Threshold
Bits 1-0 of EP2FIFOPFH are bits 9-8 of the byte count register.
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