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6.1.8.3 Simulation notes

During simulation, you may want to reduce the DCM reset time period to reduce simulation time.

The actual hardware requires a lengthy reset time that is not necessary in simulation. IN the

ii_quixote_clocks.vhd file, you will see a state machine for reseting the DCM that waits for for 2^12

clocks during reset. A line used during simulation is included that reduces this to 2^3. Just be

sure to return it to the long value when you compile for real hardware.

The simulator must be set to ps resolution for the DCMs to work properly. At lower resolution the

clocks will appear not to work.

6.1.9 Making the logic image for downloading

The Quxiote logic image may be downloaded either over the PCI bus or by using the Xilinx JTAG

port. The image must be downloaded each time the board is powered up; there is no on-board

ROM for the application logic.

6.1.9.1 Loading over PCI

To download the logic using the PCI bus, the VelociaDownload.exe application is used, or one of

the software methods discussed in the software manuals. The image must be an EXO type

(Motorola EXORMacs type).

This EXO file is created using the Xilinx IMPACT tool from the BIT file that the tools generated

after place and route was completed. See section entitled “Making the Device Image”.

6.1.9.2 Loading over JTAG

The application logic may also be downloaded over the JTAG port to the device at any time.

Connect the Xilinx cable to JP2 (see hardware manual for location and pin out).

Xilinx IMPACT software is used to load the image. When you open the IMPACT tool, you can

select the download to device in the wizard and this will lead you through the process. The JTAG

chain will identify only the application logic device and you will assign the BIT file created by the

ISE tool to load the image.

6.1.10 Pitfalls, Gotchas and Tips

Clock domains and the proper use of transition logic is the biggest problem. Carefully review the

clocks in your design and the clock discussion in this manual.

One other common problem is getting the DSP interface to reliably deliver data. Keep in mind

that the CE decodes do not show when data is available. They can remain active between

accesses if the DSP is not accessing another memory space. They are decodes, not enables.

Use ARE. AOE and AWE to qualify the accesses.

The example design uses several resets for the board, DSP and logic. This helps to be sure that

the logic is properly reset with the device it is communicating with. The board reset is essentially

the power on reset, while the other two are specific to the DSP being reset and the logic reset

controlled by the DSP.

The DSP EMIF clocks are not synchronous to each other. They are the same rate, but are not in

phase. They may also drift over time. Treat each as a unique clock.

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