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5.3 Making the Physical Logic

After the logic has been created, either with HDL or MATLAB, it must be implemented in the logic

through a process of placing and routing the logic into the physical device. For either

development process, the physical design is done using the Xilinx tools. These tools take the

netlist created by the synthesis process or Xilinx System Generator and map it into the physical

device while meeting timing and physical constraints.

Each design has a unique set of constraints for timing and physical placement that describes the

requirements of the logic. This file is the UCF (User Constraint File) used by the design. This

UCF file is provided for each FrameWork Logic design, though it may need to be modified in

some cases for your application logic.

The Xilinx ISE tools are used for the physical logic creation. For HDL designs, these tools are

accessed through the ISE environment in the processes window as shown here. The main steps

are translate (link), map and place & route.

There a many options for each of the implementation steps which are set in the individual project

files for each FrameWork Logic example.

Since most of the chips on the products are very large, we have chosen to preserve the hierarchy

of the design during the implementation so that area constraints and incremental design approach

may be used. Area constraints allow the designer to control the placement of logic on the FPGA

chip for best timing control. With area constraints, the logic will be constrained to where you put it

and in many cases helps the tool do a better job overall.

We also recommend that you use the incremental design approach in the logic implementation

process when working with the large FPGA designs. This allows you to make minor changes to a

chip during debug and test without requiring the tool to reroute the whole design. In this way,

functions that are not affected by the change are not touched so their behavior and timing does

not change.

For MATLAB Simulink, the Xilinx System Generator icon is used to control the implementation

Innovative Integration FrameWork Logic User Guide 25

Illustration 19: Xilinx Implementation Tools

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