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5.2.2 MATLAB Simulink Use

In MATLAB, you can make new block diagrams for logic designs using the libraries for Xilinx and

the specific product. Creating a new logic diagram is often aided by starting with one of the

examples for the product you are using as a starting point. You can then drag and drop Simulink

blocks into the worksheet to build the logic functionality you need.

The two ways to use the Simulink environment are to generate an entire logic design, using the

hardware layer provided by Innovative, or to make logic components that are incorporated into

your VHDL design. When building an entire logic design, you are using the hardware interface

layer as given in the top level of the application logic found in the

C:\MATLAB7\toolbox\sysgen\jtagcosim\Innovative_product_name directory. You

can also see the underlying VHDL for the components in the library in this directory. They are

used during the compilation process by Xilinx System Generator.

When you are using the environment to generate a logic block used in a VHDL design, it may well

be independent of any specific hardware design. The Simulink blocks used in these designs will

essentially be linked together and compiled, resulting an .NGC netlist file that is linked into the top

level VHDL design. Keep in mind that this is a black box approach and the resulting block can be

simulated only at the component level by using NETGEN to create VHDL for the simulation. The

VHDL from NETGEN will be hard to understand, so the debug of the block should be done in

MATLAB prior to use.

You are always required to include the Xilinx System Generator logic block to provide the link to

the Xilinx tools. This is shown in the following diagram. Through this block, you can control the

compilation and fitting process for the logic design. All options normally available for the Xilinx

PAR tools are made available through this block.

Innovative Integration FrameWork Logic User Guide 22

Illustration 15: Building a Simulink Project

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