Cypress Semiconductor Perform CY7C1372D Guia do Utilizador descarregar pdf (Página 53)

The clocks buffering, phase lock components and distribution is controlled in the ii_quixote_clocks

component in the logic. The system clock, commonly used for user application logic, is d_clk and

is 100 MHz as designed in the example logic may be easily modified in custom logic designs.

6.1.4.3.2 Domains

The following diagram shows the clock domains for the Framework Logic. Each clock domain

transition has been chosen to occur at FIFO boundaries since the FIFOs support asynchronous

clocks. This greatly simplifies the clock domain transitions in a clean way. As can be seen from

the clock domain diagram, the the EMIF B clock is used solely for the EMIF B pass-through.

While it may be the same frequency as EMIF A, there is no guarantee that the two clocks are in-

phase.

6.1.4.4 A/D Interface

The Quxiote A/D interface uses a hardware interface component for the physical interface to the

A/D and external FIFO, ii_quixote_adc.vhd, and a support component in the application logic for

triggering, error correction and data flow control, ad_interface.vhd.

Here is a block digram of the A/D interface.

Innovative Integration FrameWork Logic User Guide 53

Illustration 45: Quixote Logic Clock Domains

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