Cypress Semiconductor Perform CY7C1372D Guia do Utilizador descarregar pdf (Página 41)

to pre-trigger or post-trigger in the software which makes trigger design easier.

Here is one of the common cables used for debug, just for reference.

CAUTION:

The user MUST make sure that Xilinx JTAG cable connector is plugged in the proper

polarity to the Innovative target connector. If by mistake, the user connects the Xilinx

cable incorrectly, this may damage the target card and Xilinx POD. See the hardware

manual for each product to locate the connector and its pinout.

Innovative Integration FrameWork Logic User Guide 41

Illustration 37: Xilinx Parallel IV Cable for Debug and Development

Illustration 38: Xilinx Parallel Cable IV Target Cable

Illustration 39: Xilinx Parallel Cable IV Pinout on IDC 5x2 2MM

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Cypress Semiconductor Perform CY7C1372D Guia do Utilizador Página 41