Cypress Semiconductor Perform CY7C1372D Guia do Utilizador descarregar pdf (Página 57)

needed. Normally, this is set by the DMA channel.

Since there are very few timing adjustments in the DSP EMIF control for sync registers, logic

designers should be aware that burst interfaces require that the logic levels be minimized to meet

timings. The Quixote logic has a simple data decoding and mux structure that allows the burst

memories high speed, while penalizing slower async devices with a extra cycles for decoding and

data delivery. Even then, only a small portion of the ACE0 memory space are read-back registers

because of the speed required. These read registers are grouped in the memory map so that a

minimum of logic must be decoded and thereby maximizing the speed. Adding new read-back

registers therefore should be done in a small memory region, requiring minimum logic.

The DSP memory is easily subdivided into memory types, such as async and burst by using

different CE spaces. The DSP gives four CE signals for each EMIF that have timings as defined

by the software (EMIF control registers) The memory map for the Framework Logic uses is shown

in section 5.1.4.2.

Inside of the DSP EMIF A component (ii_quxiote_dsp_emif_a.vhd), you can see how the

decoding, FIFOs and data readback are done. For speed, all signals are registered as they enter

Innovative Integration FrameWork Logic User Guide 57

Illustration 49: TI DSP Synchronous Memory Read Interface (Courtesy of

Texas Instruments).

Illustration 50: TI DSP Synchronous Memory Write Interface (Courtesy of

Texas Instruments).

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