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7.1.1.7 ii_quixote_clocks

Supported Platforms: Quixote

Description:

This component provides the clocks for the application logic and external devices. The DSP EMIF

clock inputs are phase locked to improve timing by reducing skew on-chip. The other clocks are

put onto bufg components for use by the logic.

The PLL clock, from the on-board PLL device, is received by the FPGA clock component. It is

divided by two in the logic to reduce the clock range to 15-150 Mhz for use by the logic since the

PLL output range is 30-300 Mhz. The minimum clock rate for the A/D is 15 Mhz so this matches

that requirement also.

The reference clock is a 10 Mhz input clock used as a timebase internally. The phase-lock clock

components, Xilinx DCMs, require a specific time period for proper reset once the input clock is

present. The reference clock is used for the DCM reset timing since it is always available.

Innovative Integration FrameWork Logic User Guide 91

Illustration 63: ii_quixote_clocks Block Diagram

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