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CYV15G0404DXB Evaluation Board

Users Guide

Page 26 of 56

Note. The output of the DG2020 for this PDA file are mapped to POD-A bits 0–11. If outputs need to be remapped for a particular

test set-up, consult the DG2020 user’s manual.

2. Using the bit assignment scheme in Table 7-4, connect two TXDATA parallel cables from the DG2020 to J1C and J2C (TX-

DATA[9:0] to TXDC[7:0] and TXCTC[1:0]). Connect two more TXDATA cables from the DG2020 to J1D and J2D using the

same assignment scheme.

3. Connect two REFCLK lines of the DG2020 to REFCLKC+ (J12C) and REFCLKD+ (J12D). Make sure the oscillators (Y1C and

Y1D) are disconnected. This test is using the single-ended SMA clock option for both channels (see Section 6.4 on page 18)

4. Connect the Logic Analyzer TDA700 to read the receive data lines on J5C for RXDC[7:0] and on J6C for RXSTC[2:0]. Follow

the bit assignment in Table 7-5

5. Connect a clock input of the logic analyzer to RXCLKC on J17C. The clocking of the logic analyzer needs to set to external.

On the TDA700 series logic analyzer, go to the “SET-UP” window. After selecting external clocking, press the “MORE” button

to customize your clock's settings. Your clock definition needs to be set to the RXCLKC input.

6. Connect a pair of serial outputs (SEROUTD1/SEROUTD1) to the digital signal analyzer using SMA cables.

7. Trigger the analyzer by connecting an SMA-to-SMA cable from TXCLKOD (J10D) to the trigger input of the analyzer.

8. Adjust the power supply to 3.3 volts and 3 amps limit and apply power to the board and the device.

9. Verify that the power supply LED’s (D6 and DT6) are on.

10.Set SPDSELC = HIGH and SPDSELD = HIGH. Set ULCx

= HIGH, LPENx = HIGH for internal loopback, and RCLKENx = LOW.

11.Start transmitting data from the data generator, making sure it is in REPEAT mode.

12.Make sure the jumpers for WREN

(J39) and RESET(J40) are set HIGH to enable the push buttons (see Figure 6-3 on page 17).

13.Press and release RESET

to reset the board.

14.Configure the control latches as listed in Table 7-6 for addresses 6 (0110b) through 11 (1011b) for channels C and D.

Table 7-4. Input Register Bit Assignments

Signal Name Unencoded

TXDx0 (LSB) TXDATA0

TXDx1 TXDATA1

TXDx2 TXDATA2

TXDx3 TXDATA3

TXDx4 TXDATA4

TXDx5 TXDATA5

TXDx6 TXDATA6

TXDx7 TXDATA7

TXCTx0 TXDATA8

TXCTx1 (MSB) TXDATA9

Table 7-5. Output Register Bit Assignments

Signal Name

BYPASS ACTIVE

(DECBYP = 0)

RXSTC2 (LSB) COMDET

RXSTC1 DATA0

RXSTC0 DATA1

RXDC0 DATA2

RXDC1 DATA3

RXDC2 DATA4

RXDC3 DATA5

RXDC4 DATA6

RXDC5 DATA7

RXDC6 DATA8

RXDC7 (MSB) DATA9

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