Cypress Semiconductor CYV15G0404DXB Guia do Utilizador descarregar pdf (Página 23)

CYV15G0404DXB Evaluation Board

Users Guide

Page 23 of 56

1. Ensure that there are no SMA cables connected to the REFCLKx inputs. Make sure the oscillators are all connected to their

respective 14-pin DIP sockets. This test is using the Crystal Oscillator clock option (see Section 6.4 on page 18). Make sure

channel A is running at 125 MHz, channel B at 106.25 MHz, channel C at 27 MHz, and channel D at 20 MHz.

2. Adjust Power Supply to 3.3V and 3A limit. Apply power to the board and device.

3. Verify that the power supply LEDs (D6 and DT6) are on.

4. Place jumpers on J31–J34 so that SPDSELA = HIGH, SPDSELB = HIGH, SPDSELC = LOW and SPDSELD = LOW (see

Figure 6-1 on page 17).

5. Set LPENx (A,B,C,D) to HIGH, ULCx

to HIGH, and RCLKENx to LOW.

6. Make sure the jumpers for WREN (J39) and RESET(J40) are configured to enable the push buttons (see Figure 6-3 on page

17).

7. Press and release the RESET

button.

8. Verify that the LFIx

LED’s are all on.

To prevent the Channel A latches from being affected by the global configuration, the Global Enable Control bits for Channel A

(GLEN0, GLEN1, and GLEN2) need to be set to 0. All of these control bits are located at bit 0 of each address. To leave the other

Channel A latches (bits 1 to 7) in their original states, they need to be masked out by following the next step.

9. Set ADDR[3:0] =1111 to select the mask latch bank. Set DATA[7:0] = 00000001 to mask out bits 1 to 7. Press the WREN

button.

10.To change GLEN0, set ADDR[3:0] = 0000 and DATA[7:0] = 00000000. Press WREN

. This will only change GLEN0 to 0.

11.Follow the same procedure as in step 10 to set both GLEN1 (ADDR[3:0] = 0001) and GLEN2 (ADDR[3:0] =0010) to 0.

12.Remove all the masks by setting ADDR[3:0] =1111 and DATA[7:0] = 11111111. Press WREN

13.To run the BIST on Channels B, C, and D, configure the control signals according to the configuration table below. Note:

FGLEN0, FGLEN1, and FGLEN2 are all 0 so that Channel A is not altered. Colored background = 1, white = 0.

The following steps are for result verification of the four channel BIST:

14.Verify that the LED’s for LFIB

, LFIC, and LFID, are now off. The LFIA LED should still be on.

15.Check the RXSTx1 signal for all four channels. RXSTA1 should always be LOW because its BIST wasn’t enabled. RXSTB1

should have pulses of approximately 9.4-ns width and 4.9-µs period. RXSTC1 should have pulses of approximately 37.0-ns

width and 19.4-µs period and RXSTD1 should have pulses of approximately 50.0-ns width and 26.3-µs period.

16.Verify that RXSTB2, RXSTC2, and RXSTD2 remain low to indicate that there are no BIST errors.

17.To force all channels (including channel A) to run a BIST, run the same configuration as in step 13, but with FGLEN0, FGLEN1,

and FGLEN2 set to 1.

18.Verify that the LFIA

LED turns off.

19.Check that RXSTA1 has pulses of approximately 8-ns width and 4.2-µs period.

20.Verify that RXSTA2 remains low to indicate that there are no BIST errors.

7.2 Parallel Data Test Mode

7.2.1 Equipment Required

Equipment needed:

• CYV15G0404DXB evaluation board

• Instrument-grade power supply 3 Amp @ 3.3V

• Parallel Data Generator: DG2020 from TekTronix (settings will be provided by Cypress) or equivalent

• Logic Analyzer: TDA700 series from TekTronix or equivalent.

Table 7-2. Device Control Latch Configuration Table for Global Configuration

ADDR Chnl Type DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Reset Value

(1100b)

GLBL S RFMODE

GL[1] =’1’

RFMODE

GL[0] = ‘0’

FRAMCHAR

GL = ‘1’

DECMODE

GL = ‘1’

DECBYP

GL = ‘1’

RXCKSEL

GL = ‘1’

RXRATE

GL = ‘0’

FGLEN0

=’0’

N/A

(1101b)

GLBL S

SDASEL2

GL[1] = ‘1’

SDASEL2

GL[0] = ‘0’

SDASEL1

GL[1] = ‘1’

SDASEL1

GL[0] =’0’

ENCBYP

GL = ‘1’

TXCKSEL

GL = ‘1’

TXRATE

GL = ‘0’

FGLEN1

=’0’

N/A

(1110b)

GLBL D

RFEN

GL =’1’

RXPLLPD

GL = ‘1’

RXBIST

GL = ‘0’

TXBIST

GL =’0’

OE2

GL = ‘1’

OE1

GL = ‘1’

PABRST

GL = ‘0’

FGLEN2

=‘0’

N/A

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