Cypress Semiconductor CY7B9910 Manual do Utilizador descarregar pdf

Low Skew

Clock Buffer

CY7B9910

CY7B9920

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600

November 1994 - Revised Jul

1997

Features

• All outputs skew <100 ps typical (250 max.)

• 15- to 80-MHz output operation

• Zero input to output delay

• 50% duty-cycle outputs

•

Outputs drive 50

Ω

terminated lines

• Low operating current

• 24-pin SOIC package

• Jitter: <200 ps peak to peak, <25 ps RMS

• Compatible with Pentium™-based processors

Functional Description

The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer

low-skew system clock distribution. These multiple-output

clock drivers optimize the timing of high-performance comput-

er systems. Eight individual drivers can each drive terminated

transmission lines with impedances as low as 50

Ω

while deliv-

ering minimal and specified output skews and full-swing logic

levels (CY7B9910 TTL or CY7B9920 CMOS).

The completely integrated PLL allows “zero delay” capability.

External divide capability, combined with the internal PLL, allows

distribution of a low-frequency clock that can be multiplied by virtu-

ally any factor at the clock destination. This facility minimizes clock

distribution difficulty while allowing maximum system clock speed

and flexibility.

Block Diagram Description

Phase Frequency Detector and Filter

These two blocks accept inputs from the reference frequency

(REF) input and the feedback (FB) input and generate correc-

tion information to control the frequency of the Voltage-Con-

trolled Oscillator (VCO). These blocks, along with the VCO,

form a Phase-Locked Loop (PLL) that tracks the incoming

REF signal.

VCO

The VCO accepts analog control inputs from the PLL filter

block and generates a frequency. The operational range of the

VCO is determined by the FS control pin.

Test Mode

The TEST input is a three-level input. In normal system oper-

ation, this pin is connected to ground, allowing the

CY7B9910/CY7B9920 to operate as explained above. (For

testing purposes, any of the three-level inputs can have a re-

movable jumper to ground, or be tied LOW through a 100

Ω

resistor. This will allow an external tester to change the state of

these pins.)

If the TEST input is forced to its MID or HIGH state, the device

will operate with its internal phase-locked loop disconnected,

and input levels supplied to REF will directly control all outputs.

Relative output to output functions are the same as in normal

mode.

Pentium is a trademark of Intel Corporation.

Logic Block Diagram Pin Configuration

7B9910–1

7B9910–2

TEST

REF

Voltage

Controlled

Oscillator

FILTER

PHASE

FREQ

DET

REF

CCQ

CCN

GND

CCN

GND

TEST

GND

CCN

GND

CCN

SOIC

Top View

7B9910

7B9920

1 2 3 4 5 6 7 8

Resumo do Conteúdo

Página 1 - Clock Buffer

Low SkewClock BufferCY7B9910CY7B9920 Cypress Semiconductor Corporation• 3901 North First Street • San Jose • CA 95134 • 408-943-2600November 1994 - Re

Página 2 - CY7B9920

CY7B9910CY7B99202Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Storage Temperature ...

Página 3

CY7B9910CY7B99203IILLInput LOW Current (Test, FS)VIN = GND –200 –200µAIOSOutput Short Circuit Current[2]VCC = Max., VOUT = GND (25°C only)–250 N/A mA

Página 4

CY7B9910CY7B99204AC Test Loads and Waveforms7B9910–37B9910–4TTL AC Test Load (CY7B9910) TTL Input Test Waveform (Cy7B9910)5VR1R2CLR1R2CL7B9910–5CMOS

Página 5

CY7B9910CY7B99205tOFALLOutput Fall Time[17, 18]0.15 1.0 1.5 0.5 2.0 3.0 nstLOCKPLL Lock Time[19]0.5 0.5 mstJRCycle-to-Cycle Output Jitter Peak to Pea

Página 6

CY7B9910CY7B99206AC Timing DiagramstODCVtODCVtREFREFFBQOTHERQtRPWHtRPWLtPDtSKEWtSKEWtJR7B9910–8

Página 7 - CY7B9910

CY7B9910CY7B9920© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor

Página 8

CY7B9910CY7B99208Document #: 38–00437–BOrdering InformationAccuracy(ps)Ordering CodePackageNamePackage TypeOperatingRange250 CY7B9910–2SC S13 24-Lead

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Cypress Semiconductor CY7B9910 Manual do Utilizador

Consulte online ou descarregue Manual do Utilizador para Relógios de parede Cypress Semiconductor CY7B9910. CY7B9910, 9920 [en] Manual do Utilizador

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