Cypress Semiconductor CYV15G0404DXB Guia do Utilizador Página 16
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CYV15G0404DXB Evaluation Board
Users Guide
Page 16 of 56
Table 5-4 shows the mapping of latches in the device. Each row of the table is defined by an address, ADDR[3:0]. The Chnl
column lists the channel being configured for the particular address. The Type column lists whether the signals for the particular
address are static or dynamic. A detailed description of the latch types is in the datasheet. The data signals DATA[7:0] will
determine the value of the respective control latches upon assertion. The Reset Value of an address is the value in the latch
bank of that address after a global reset. For example, at address 0 (0000b), the reset value is 10111111. Thus, RFMODEA1 =
1, RFMODEA0 = 0, FRAMCHARA=1, DECMODEA = 1, DECBYPA = 1, RXCKSELA = 1, RXRATEA = 1, and GLEN0 = 1.
OE1x Primary Differential Serial Data Output Driver Enable
• When 1, the output driver is enabled allowing data to be transmitted
• When 0, the output driver is disabled
PABRSTx Transmit Clock Phase Alignment Buffer Reset
• When a 0 is written, the phase of TXCLKx relative to REFCLKx is initialized
• This is a self clearing latch, eliminating the requirement of writing a 1 to complete the initialization
of the Phase Alignment Buffer
GLEN[11..0] Global Enable
• When 1 for a given address, that address can participate in a global configuration
• When 0 for a given address, that address will not participate in a global configuration
FGLEN[2..0] Force Global Enable
• When 1 for the associated global channel, FGLEN forces the global update of the target latch banks
Table 5-4. Device Control Latch Configuration
ADDR Chnl Type DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
Reset
Value
0
(0000b)
ASRFMODE
A[1]
RFMODE
A[0]
FRAMCHAR
A
DECMODE
A
DECBYP
A
RXCKSEL
A
RXRATE
A
GLEN0 10111111
1
(0001b)
A S SDASEL2
A[1]
SDASEL2
A[0]
SDASEL1
A[1]
SDASEL1
A[0]
ENCBYP
A
TXCKSEL
A
TXRATE
A
GLEN1 10101101
2
(0010b)
ADRFEN
A
RXPLLPD
A
RXBIST
A
TXBIST
A
OE2
A
OE1
A
PABRST
A
GLEN2 10110011
3
(0011b)
BSRFMODE
B[1]
RFMODE
B[0]
FRAMCHAR
B
DECMODE
B
DECBYP
B
RXCKSEL
B
RXRATE
B
GLEN3 10111111
4
(0100b)
B S SDASEL2
B[1]
SDASEL2
B[0]
SDASEL1
B[1]
SDASEL1
B[0]
ENCBYP
B
TXCKSEL
B
TXRATE
B
GLEN4 10101101
5
(0101b)
BDRFEN
B
RXPLLPD
B
RXBIST
B
TXBIST
B
OE2
B
OE1
B
PABRST
B
GLEN5 10110011
6
(0110b)
CSRFMODE
C[1]
RFMODE
C[0]
FRAMCHAR
C
DECMODE
C
DECBYP
C
RXCKSEL
C
RXRATE
C
GLEN6 10111111
7
(0111b)
C S SDASEL2
C[1]
SDASEL2
C[0]
SDASEL1
C[1]
SDASEL1
C[0]
ENCBYP
C
TXCKSEL
C
TXRATE
C
GLEN7 10101101
8
(1000b)
CDRFEN
C
RXPLLPD
C
RXBIST
C
TXBIST
C
OE2
C
OE1
C
PABRST
C
GLEN8 10110011
9
(1001b)
DSRFMODE
D[1]
RFMODE
D[0]
FRAMCHAR
D
DECMODE
D
DECBYP
D
RXCKSEL
D
RXRATE
D
GLEN9 10111111
10
(1010b)
D S SDASEL2
D[1]
SDASEL2
D[0]
SDASEL1
D[1]
SDASEL1
D[0]
ENCBYP
D
TXCKSEL
D
TXRATE
D
GLEN10 10101101
11
(1011b)
DDRFEN
D
RXPLLPD
D
RXBIST
D
TXBIST
D
OE2
D
OE1
D
PABRST
D
GLEN11 10110011
12
(1100b)
GLBL S RFMODE
GL[1]
RFMODE
GL[0]
FRAMCHAR
GL
DECMODE
GL
DECBYP
GL
RXCKSEL
GL
RXRATE
GL
FGLEN0 N/A
13
(1101b)
GLBL S SDASEL2
GL[1]
SDASEL2
GL[0]
SDASEL1
GL[1]
SDASEL1
GL[0]
ENCBYP
GL
TXCKSEL
GL
TXRATE
GL
FGLEN1 N/A
14
(1110b)
GLBL D RFEN
GL
RXPLLPD
GL
RXBIST
GL
TXBIST
GL
OE2
GL
OE1
GL
PABRST
GL
FGLEN2 N/A
15
(1111b)
All
Mask
D D7 D6 D5 D4 D3 D2 D1 D0 11111111
Table 5-3. Device Control Latch Description (continued)
Pin Name Characteristics
[+] Feedback
- , CA 95134 • 408-943-2600 1
- Users Guide 3
- Page 3 of 56 3
- Page 4 of 56 4
- 1.0 Overview 5
- 2.0 Kit Contents 5
- Transmit Path Block Diagram 7
- Receive Path Block Diagram 8
- Channel C I/O (see Fig. 5) 10
- [+] Feedback 11
- 6.1 Speed Select Jumpers 17
- 6.2 DIP Switches 17
- 7.0 Test Modes 19
- Parallel Data Test Mode 23
- REFCLK50 24
- (100 MHz.) 25
- 7.3 Reclocker Test Mode 27
- Page 30 of 56 30
- Page 31 of 56 31
- Page 32 of 56 32
- Page 33 of 56 33
- Page 34 of 56 34
- Page 35 of 56 35
- Page 36 of 56 36
- Page 37 of 56 37
- Appendix B: PCB Layout for 38
- Page 39 of 56 39
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- Page 55 of 56 55
- Mouser Electronics 57
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