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CYV15G0404DXB Evaluation Board

Users Guide

Page 20 of 56

Cables needed:

• SMA to SMA coaxial cables

• Power supply cables (banana plug cables).

7.1.1.2 Test Equipment Set-up

Figure 7-2 shows the test set-up for BIST on channel A. The signal analyzer in the diagram is optional. See Section 6.4 on page

18 for REFCLKx input options. The BIST tests will use the Crystal Oscillator option. To use the optional pulse generator instead

of the supplied oscillators, connect an SMA-to-SMA cable using the single-ended SMA option (see Section 6.4 on page 18). If

using the pulse generator, make sure the SPDSELx control is set correctly (see Section 6.1 on page 17).

7.1.1.3 Test Set-up

The intention of this set-up is to test the CYV15G0404DXB in BIST mode. For this test, the device will transmit BIST data across

Channel A and receive the same BIST data across the same channel by looping back the serial data within the device (referred

to as Internal Loopback mode). Follow the procedure below for the test set-up.

1. Ensure that there are no SMA cables connected to the REFCLKA± inputs. Make sure the 125 MHz oscillator is connected to

the14-pin DIP socket for Channel A. This test is using the Crystal Oscillator clock option (see Section 6.4 on page 18).

2. Adjust the power supply to 3.3V and 3A limit. Apply power to the board and chip by connecting 3.3V banana plugs to J48 and

J50. Connect a banana plug from ground on the power supply to J49.

3. Verify that the power supply LEDs (D6 and DT6) are on.

4. Set SPDSELA to HIGH (see Figure 6-1 on page 17).

5. Set LPENA(S2) to HIGH, ULCA

(S3) to HIGH, and RCLKENA(S7) to LOW. The value of INSELx does not matter during internal

loopback mode.

6. Make sure the jumpers for WREN

(J39) and RESET(J40) are configured to enable the push buttons (see Figure 6-3 on page

17).

7. Press and release RESET

to reset the board.

8. Verify that all LFIx

LEDs are ON, indicating line faults on all channels.

9. Configure the control signals for channel A according to the configuration table below (refer to Section 6.3 on page 17).

3.3V 3.0A

Power Supply

3.3V GND

3.3V

GND

Signal Analyzer

Ext Trigger

Input

Oscilloscope

Input

TXCLKOA

SEROUTA1

RXSTA[2:1]

Evaluation Board

CYV15G0404DX

Figure 7-2. Pictorial Representation of the Internal BIST Set-up

Pulse Generator

Output REFCLKA

Vcc

OSC

3.3V

[+] Feedback

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 56 57

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