Cypress Semiconductor CYV15G0404DXB Guia do Utilizador Página 11

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CYV15G0404DXB Evaluation Board
Users Guide
Page 11 of 56
Figure 5-2 shows the parallel I/O and reference clock connectors for channel A. Channels B, C, and D have a similar layout of
connectors. Note that TXERR is not located at the same position for the other channels. Refer to Figure 5-1 for their locations.
Table 5-1 gives a brief description of the connectors on the evaluation board. An “x” following a connector or signal name
represents all four channels; e.g., Connector J1x for TXDx represents the connectors J1A, J1B, J1C, and J1D for the buses
TXDA[7:0], TXDB[7:0], TXDC[7:0], and TXDD[7:0], respectively. For a more detailed description of the connectors and signals,
refer to the data sheet.
Table 5-1. Description of Connectors of the CYV15G0404DXB Evaluation Board
Connectors Signals Description
J1x TXDx[7:0] LVTTL Input
Transmit parallel data input for channel x
J2x TXCTx[1:0] LVTTL Input
Transmit control signals for channel x
J3x TXCLKx LVTTL Input
Transmit clock input for channel x
J4x TXCLKOx LVTTL Output
Buffered version of internal character rate clock
J5x RXDx[7:0] LVTTL Output
Receive parallel data output for channel x
J6x RXSTx[2:0] LVTTL Output
Receive parallel data status output for channel x
J7x RXCLKx- LVTTL Output
Complement of recovered clock at the receiver for channel x
J8x RXCLKx+ LVTTL Output
Recovered clock at the receiver for channel x
J9x TXERRx LVTTL Output
Transmit path error signal for channel x
J10x TXCLKOx SMA Connector for TXCLKOx
Buffered version of internal character rate clock
J11x REFCLKx+ SMA Connector for REFCLKx +
Positive input of reference clock for channel x
Figure 5-2. Channel A Connectors
J1A(TXDA)
J2A(TXCTA)
J3A(TXCLKA)
J4A(TXCLKOA)
J5A(RXDA)
J6A(RXSTA)
J7A(RXCLKA-)
J8A(RXCLKA+
)
J9A(TXERRA)
SMA)
J10A(TXCKLOA
J12A(REFCLKA-
SMA)
J18A(REFCLKA)
J11A(REFCLKA
+
SMA)
J17A(RXCLKA+
SMA)
Y1A(OSC)
[+] Feedback
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