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Programmable Skew Clock Buffer

CY7B991

CY7B992

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600

November 1991 - Revised Jul

1997

Features

• All output pair skew <100 ps typical (250 max.)

• 3.75- to 80-MHz output operation

• User-selectable output functions

— Selectable skew to 18 ns

— Inverted and non-inverted

— Operation at

⁄

and

⁄

input frequency

— Operation at 2x and 4x input frequency (input as low

as 3.75 MHz)

• Zero input to output delay

• 50% duty-cycle outputs

•

Outputs drive 50

Ω

terminated lines

• Low operating current

• 32-pin PLCC/LCC package

• Jitter < 200 ps peak-to-peak (< 25 ps RMS)

• Compatible with a Pentium™-based processor

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buff-

ers (PSCB) offer user-selectable control over system clock

functions. These multiple-output clock drivers provide the sys-

tem integrator with functions necessary to optimize the timing

of high-performance computer systems. Eight individual driv-

ers, arranged as four pairs of user-controllable outputs, can

each drive terminated transmission lines with impedances as

low as 50

Ω

while delivering minimal and specified output skews

and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).

Each output can be hardwired to one of nine delay or function

configurations. Delay increments of 0.7 to 1.5 ns are deter-

mined by the operating frequency with outputs able to skew up

6 time units from their nominal “zero” skew position. The com-

pletely integrated PLL allows external load and transmission line

delay effects to be canceled. When this “zero delay” capability of the

PSCB is combined with the selectable output skew functions, the

user can create output-to-output delays of up to

12 time units.

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems.

When combined with the internal PLL, these divide functions

allow distribution of a low-frequency clock that can be multi-

plied by two or four at the clock destination. This facility mini-

mizes clock distribution difficulty while allowing maximum sys-

tem clock speed and flexibility.

Pentium is a trademark of Intel Corporation.

Logic Block Diagram Pin Configuration

7B991–1

7B991–2

TEST

REF

VCO AND

TIME UNIT

GENERATOR

SELECT

INPUTS

(THREE

LEVEL)

SKEW

SELECT

MATRIX

1234323130

17161514 18 19 20

3F0

REF

GND

TEST

2F1

2Q1

2Q0

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

CCQ

2F0

GND

1F1

1F0

CCN

1Q0

1Q1

GND

3Q1

3Q0

CCN

3F1

4F0

4F1

CCQ

CCN

4Q1

4Q0

GND

PLCC/LCC

CY7B991

CY7B992

FILTER

PHASE

FREQ

DET

1 2 3 4 5 6 ... 13 14

Resumo do Conteúdo

Página 1 - Functional Description

Programmable Skew Clock BufferCY7B991CY7B992 Cypress Semiconductor Corporation• 3901 North First Street • San Jose • CA 95134 • 408-943-2600November 1

Página 2 - Pin Definitions

CY7B991CY7B99210Operational Mode DescriptionsFigure 2 shows the PSCB configured as a zero-skew clockbuffer. In this mode the 7B991/992 can be used as

Página 3 - Operating Range

CY7B991CY7B992113F0 = MID, and 3F1 = High. (Since FB aligns at –4 tU and 3Qxskews to +6 tU, a total of +10 tU skew is realized.) Many other con-figura

Página 4 - Electrical Characteristics

CY7B991CY7B99212Figure 8 shows the CY7B991/992 connected in series to con-struct a zero-skew clock distribution tree between boards. De-lays of the do

Página 5 - AC Test Loads and Waveforms

CY7B991CY7B99213MILITARY SPECIFICATIONSGroup A Subgroup TestingDocument #: 38–00513–AOrdering InformationAccuracy(ps)Ordering CodePackageNamePackage T

Página 6 - Switching Characteristics

CY7B991CY7B992© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor

Página 7

CY7B991CY7B9922Block Diagram DescriptionPhase Frequency Detector and FilterThese two blocks accept inputs from the reference frequency(REF) input and

Página 8

CY7B991CY7B9923Test ModeThe TEST input is a three-level input. In normal system oper-ation, this pin is connected to ground, allowing theCY7B991/CY7B9

Página 9 - AC Timing Diagrams

CY7B991CY7B9924Electrical Characteristics Over the Operating Range[6]CY7B991 CY7B992Parameter Description Test Conditions Min. Max. Min. Max. UnitVOHO

Página 10 - Operational Mode Descriptions

CY7B991CY7B9925Capacitance[12]Parameter Description Test Conditions Max. UnitCINInput Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V 10 pFNote:12. Appli

Página 11 - Figure 7

CY7B991CY7B9926Switching Characteristics Over the Operating Range[2, 13]CY7B991–2[14]CY7B992–2[14]Parameter Description Min. Typ. Max. Min. Typ. Max.

Página 12 - Figure 8

CY7B991CY7B9927Switching Characteristics Over the Operating Range[2, 13] (continued)CY7B991–5 CY7B992–5Parameter Description Min. Typ. Max. Min. Typ.

Página 13 - MILITARY SPECIFICATIONS

CY7B991CY7B9928Switching Characteristics Over the Operating Range[2, 13] (continued)CY7B991–7 CY7B992–7Parameter Description Min. Typ. Max. Min. Typ.

Página 14 - CY7B991

CY7B991CY7B9929AC Timing DiagramstODCVtODCVtREFREFFBQOTHERQINVERTED QREF DIVIDED BY 2REF DIVIDED BY 47B991–8tRPWHtRPWLtPDtSKEWPR,tSKEW0,1tSKEWPR,tSKEW

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Cypress Semiconductor CY7B991 Manual do Utilizador

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