Cypress Semiconductor Quad HOTLink II CYV15G0404RB Guia do Utilizador descarregar pdf (Página 9)

Quad Independent Channel

HOTLink II™ CYV15G0404DXB

Video PHY Demonstration Board

Page 9 of 92

Note. For HD-SDI transmit jitter measurements, it is recommended to avoid using the programmable clock due to the high intrinsic

jitter generated by this clock. This jitter will not influence the output jitter in reclocker mode, so the programmable clock may be

used to measure reclocked jitter generation. To measure HD-SDI transmit jitter of the HOTLink II video demo board, it is recom-

mended to use the on-board crystal oscillator.

The board allows various video test patterns to be generated by the FPGA at different rates and transmitted through serial outputs.

The selection of the pattern and data rate is made through the USB host interface GUI. Clock configuration instructions are given

in Figure 4-3.

If the programmable clock option is selected, the data rate setting in the GUI controls the output frequency of the programmable

clock. If the external clock option is selected, the user must ensure that the external clock frequency matches the data rate setting

in the GUI. For HD-SDI, either a full-rate (148.5 MHz or 148.5/1.001 MHz) or half-rate (74.25 MHz or 74.25/1.001 MHz) clock

may be used. If the on-board 74.25-MHz crystal oscillator option is selected, the GUI must be set to 1485 Mb/s and the FR (Full-

Rate) box should be left unchecked.

For further details on jitter measurement, please see application note entitled, SDI SMPTE Jitter Performance of the Independent

Channel HOTLink II



Transceiver.

Configuration instructions for the different clocking options are found in Figure 4-3.

Figure 4-2. Placement of Clocks on the Board

Programmable

Clocks for Each

Channel

(U13)

(U12)

(U11)

(U10)

B (JP13)

C (JP12)

A (JP11)

D (JP10)

Clock Config

Headers for

Each

Channel

27 MHz Crystal

Oscillator (reference for

programmable clocks)

(X1)

74.25 MHz

Crystal

Oscillators

B (X2)

A (X5)

D (X3)

C (X4)

1 to 4

Differential

Fanout Clock

Buffer (U9)

Channel A

Channel B

Channel C

Channel D

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