Cypress Semiconductor Quad HOTLink II CYV15G0404RB Guia do Utilizador descarregar pdf (Página 11)

Quad Independent Channel

HOTLink II™ CYV15G0404DXB

Video PHY Demonstration Board

Page 11 of 92

1. Video test pattern generation. For SD-SDI, the FPGA can generate EG1 Color Bar Data, Grey Pattern, SMPTE RP178, and

SMPTE RP178 alternate SDI checkfield patterns. For HD-SDI, the FPGA can generate Color Bar Data, Grey Pattern, SMPTE

RP198, and SMPTE RP198 alternate SDI checkfield patterns.

2. Auto rate detection and clock reconfiguration. The FPGA plays an important role in automatically detecting the incoming data

rate and reconfiguring the programmable clock to the correct frequency.

The CYV15G0404DXB configuration interface (8-bit data and 4-bit address) is configured through a Cypress Microsystems PSoC

microcontroller. The PSoC receives instructions from the host PC through the on-board USB interface.

The on-board USB interface is used to control the various operating modes of the device through a flexible GUI. The USB interface

is also used to re-program the FPGA and the PSoC microcontroller.

4.4 Power Supply

The entire board is powered through a single 6V DC power supply. The 6V input is down-converted using on-board regulators to

different voltages for the various devices in the board. The kit for the board includes a compatible 6V AC wall power supply

adapter.

Figure 4-4. Placement of FPGA and Controls

HOTLink II CYV15G0404DXB (U1)

FPGA for

channels

A and B

(U2)

FPGA for channels

C and D (U3)

USB Interface

Connector (J20)

Cypress

FX2

USB

Microcontroller

(U7)

Cypress Microsystems

PSoC Microcontroller

(U14)

128-bit I2C Bus Serial EEPROM

boot EEPROM for USB micro-controller (U8)

Configuration Devices

(U4 and U5)

Processor

Supervisory

Circuit (U6)

PSoC Programming

Header for external

PSoC configuration

(JB5)

24MHz

crystal for

USB(Y1)

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