Document Number: 38-05537 Rev. *M Page 9 of 33
On the next clock rise the data presented to DQ
and DQP
(DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1354CV25 and DQ
a,b
/DQP
a,b
for
CY7C1356CV25) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into the
device and the Write is complete.
The data written during the write operation is controlled by BW
(BW
a,b,c,d
for CY7C1354CV25 and BW
a,b
for CY7C1356CV25)
signals. The CY7C1354CV25/CY7C1356CV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the write enable input (WE
) with the selected
byte write select (BW
) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
Because the CY7C1354CV25/CY7C1356CV25 are common I/O
devices, data should not be driven into the device while the
outputs are active. The output enable (OE
) can be deasserted
HIGH before presenting data to the DQ
and DQP
(DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1354CV25 and DQ
a,b
/DQP
a,b
for
CY7C1356CV25) inputs. Doing so will tri-state the output drivers.
As a safety precaution, DQ and DQP
(DQ
a,b,c,d
/DQP
a,b,c,d
for
CY7C1354CV25 and DQ
a,b
/DQP
a,b
for CY7C1356CV25) are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE
.
Burst Write Accesses
The CY7C1354CV25/CY7C1356CV25 has an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four write operations without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load the
initial address, as described in Single Write Accesses. When
ADV/LD is driven HIGH on the subsequent clock rise, the chip
enables (CE
1
, CE
2
, and CE
3
) and WE inputs are ignored and the
burst counter is incremented. The correct BW
(BW
a,b,c,d
for
CY7C1354CV25 and BW
a,b
for CY7C1356CV25) inputs must be
driven in each cycle of the burst write in order to write the correct
bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
1
, CE
2
,
and CE
3,
must remain inactive for the duration of t
ZZREC
after the
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A
1
, A
0
Second
Address
A
1
, A
0
Third
Address
A
1
, A
0
Fourth
Address
A
1
, A
0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table
(MODE = GND)
First
Address
A
1
, A
0
Second
Address
A
1
, A
0
Third
Address
A
1
, A
0
Fourth
Address
A
1
, A
0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
I
DDZZ
Sleep mode standby current ZZ V
DD
0.2 V – 50 mA
t
ZZS
Device operation to ZZ ZZ V
DD
0.2 V – 2t
CYC
ns
t
ZZREC
ZZ recovery time ZZ 0.2 V 2t
CYC
–ns
t
ZZI
ZZ active to sleep current This parameter is sampled – 2t
CYC
ns
t
RZZI
ZZ Inactive to exit sleep current This parameter is sampled 0 – ns
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