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CY7C1354CV25

CY7C1356CV25

Document Number: 38-05537 Rev. *M Page 13 of 33

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit

instruction register. All combinations are listed in the Instruction

Codes table. Three of these instructions are listed as

RESERVED and should not be used. The other five instructions

are described in detail below.

Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO balls. To execute

the instruction once it is shifted in, the TAP controller needs to be

moved into the Update-IR state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register

upon power-up or whenever the TAP controller is given a test

logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to

be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. The SAMPLE Z command puts

the output bus into a high Z state until the next command is given

during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because there

is a large difference in the clock frequencies, it is possible that

during the Capture-DR state, an input or output will undergo a

transition. The TAP may then try to capture a signal while in

transition (metastable state). This will not harm the device, but

there is no guarantee as to the value that will be captured.

Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller’s capture set-up plus

hold times (t

and t

). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or slow)

the clock during a SAMPLE/PRELOAD instruction. If this is an

issue, it is still possible to capture all other signals and simply

ignore the value of the CK and CK# captured in the boundary

scan register.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells prior

to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can

occur concurrently when required—that is, while data captured

is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO pins. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be driven

out through the system output pins. This instruction also selects

the boundary scan register to be connected for serial access

between the TDI and TDO in the shift-DR controller state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 32 33

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