Cypress Semiconductor CY7C1354CV25 Manual do Utilizador Página 20

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CY7C1354CV25
CY7C1356CV25
Document Number: 38-05537 Rev. *M Page 20 of 33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage on V
DD
relative to GND .......–0.5 V to +3.6 V
Supply voltage on V
DDQ
relative to GND ...... –0.5 V to +V
DD
DC to outputs in tri-state ...................–0.5 V to V
DDQ
+ 0.5 V
DC input voltage ................................. –0.5 V to V
DD
+ 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Latch-up current ................................................... > 200 mA
Operating Range
Range Ambient Temperature V
DD
/V
DDQ
Commercial 0 °C to +70 °C 2.5 V ± 5%
Industrial –40 °C to +85 °C
Electrical Characteristics
Over the Operating Range
Parameter
[17, 18]
Description Test Conditions Min Max Unit
V
DD
Power supply voltage 2.375 2.625 V
V
DDQ
I/O supply voltage for 2.5 V I/O 2.375 V
DD
V
V
OH
Output HIGH voltage for 2.5 V I/O, I
OH
= 1.0 mA 2.0 V
V
OL
Output LOW voltage for 2.5 V I/O, I
OL
= 1.0 mA 0.4 V
V
IH
Input HIGH voltage for 2.5 V I/O 1.7 V
DD
+ 0.3 V V
V
IL
Input LOW voltage
[17]
for 2.5 V I/O –0.3 0.7 V
I
X
Input leakage current except ZZ
and MODE
GND V
I
V
DDQ
–5 5 A
Input current of MODE Input = V
SS
–30 A
Input = V
DD
–5A
Input current of ZZ Input = V
SS
–5 A
Input = V
DD
–30A
I
OZ
Output leakage current GND V
I
V
DDQ,
output disabled –5 5 A
I
DD
V
DD
operating supply V
DD
= Max, I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
4-ns cycle,
250 MHz
–250mA
5-ns cycle,
200 MHz
–220mA
6-ns cycle,
166 MHz
–180mA
I
SB1
Automatic CE power-down
current — TTL inputs
Max V
DD
, device deselected,
V
IN
V
IH
or V
IN
V
IL
,
f = f
MAX
= 1/t
CYC
4-ns cycle,
250 MHz
–130mA
5-ns cycle,
200 MHz
–120mA
6-ns cycle,
166 MHz
–110mA
I
SB2
Automatic CE power-down
current — CMOS inputs
Max V
DD
, device deselected,
V
IN
0.3 V or V
IN
> V
DDQ
0.3 V,
f = 0
All speed
grades
–40mA
Notes
17. Overshoot: V
IH(AC)
< V
DD
+ 1.5 V (Pulse width less than t
CYC
/2), undershoot: V
IL(AC)
> –2 V (Pulse width less than t
CYC
/2).
18. T
Power-up
: Assumes a linear ramp from 0 V to V
DD
(min)
within 200 ms. During this time V
IH
< V
DD
and V
DDQ
V
DD
.
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