Cypress Semiconductor CY7C1473BV33 Manual do Utilizador

Consulte online ou descarregue Manual do Utilizador para não Cypress Semiconductor CY7C1473BV33. CY7C1471BV33/CY7C1473BV33, 72-Mbit (2 M × 36/4 M × 18) Flow Manual do Utilizador

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CY7C1471BV33
CY7C1473BV33
72-Mbit (2 M × 36/4 M × 18) Flow-Through
SRAM with NoBL™ Architecture
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-15029 Rev. *G Revised May 25, 2012
72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Arch itecture
Features
No bus latency™ (NoBL™) architecture eliminates dead cycles
between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte write capability
3.3 V/2.5 V I/O supply (V
DDQ
)
Fast clock-to-output times
6.5 ns (for 133 MHz device)
Clock enable (CEN) pin to enable clock and suspend operation
Synchronous self-timed writes
Asynchronous output enable (OE)
CY7C1471BV33 available in JEDEC-standard Pb-free 100-pin
thin quad flat pack (TQFP), Pb-free and non-Pb-free 165-ball
fine-pitch ball grid array (FBGA) package. CY7C1473BV33
available in JEDEC-standard Pb-free 100-pin thin quad flat
pack (TQFP)
Three chip enables (CE
1
, CE
2
, CE
3
) for simple depth
expansion
Automatic power-down feature available using ZZ mode or CE
deselect
IEEE 1149.1 JTAG boundary scan compatible
Burst capability – linear or interleaved burst order
Low standby power
Functional Description
The CY7C1471BV33 and CY7C1473BV33 are 3.3 V,
2 M × 36/4 M × 18 synchronous flow through burst SRAMs
designed specifically to support unlimited true back-to-back read
or write operations without the insertion of wait states. The
CY7C1471BV33 and CY7C1473BV33 are equipped with the
advanced No Bus Latency (NoBL) logic. NoBL™ is required to
enable consecutive read or write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN
) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
Write operations are controlled by two or four Byte Write Select
(BW
X
) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE
) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Description 133 MHz Unit
Maximum access time 6.5 ns
Maximum operating current 305 mA
Maximum CMOS standby current 120 mA
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Resumo do Conteúdo

Página 1 - SRAM with NoBL™ Architecture

CY7C1471BV33CY7C1473BV3372-Mbit (2 M × 36/4 M × 18) Flow-ThroughSRAM with NoBL™ ArchitectureCypress Semiconductor Corporation • 198 Champion Court • S

Página 2

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 10 of 31Truth TableThe truth table for CY7C1471BV33, and CY7C1473BV33 follows. [1, 2,

Página 3

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 11 of 31Truth Table for Read/WriteThe read/write truth table for CY7C1471BV33/CY7C147

Página 4

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 12 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1471BV33 incorporate a serial

Página 5

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 13 of 31RESERVED and must not be used. The other five instructionsare described in de

Página 6

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 14 of 31TAP Controller State DiagramTEST-LOGICRESETRUN-TEST/IDLESELECTDR-SCANSELECTIR

Página 7

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 15 of 31TAP Controller Block DiagramBypass Register0Instruction Register012Identicat

Página 8 - Single Write Accesses

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 16 of 313.3 V TAP AC Test ConditionsInput pulse levels ...

Página 9 - Linear Burst Address Table

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 17 of 31TAP AC Switching CharacteristicsOver the Operating RangeParameter [12, 13]Des

Página 10 - CY7C1473BV33

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 18 of 31Identification Register DefinitionsInstruction FieldCY7C1471BV33(2 M × 36)Des

Página 11

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 19 of 31Boundary Scan Exit Order(2 M × 36)Bit # 165-ball ID Bit # 165-ball ID Bit # 1

Página 12 - TAP Instruction Set

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 2 of 31Logic Block Diagram – CY7C1471BV33CMODEBWABWBWECE1CE2CE3OEREAD LOGICDQsDQPADQP

Página 13

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 20 of 31Maximum RatingsExceeding maximum ratings may shorten the useful life of thede

Página 14

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 21 of 31ISB4Automatic CE power-down current – TTL inputsVDD = Max, device deselected,

Página 15

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 22 of 31Switching CharacteristicsOver the Operating RangeParameter [19]Description133

Página 16

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 23 of 31Switching WaveformsFigure 5. Read/Write Timing [24, 25, 26]WRITED(A1)1234567

Página 17

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 24 of 31Figure 6. NOP, STALL, and DESELECT Cycles [27, 28, 29]Switching Waveforms (c

Página 18

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 25 of 31Figure 7. ZZ Mode Timing [30, 31]Switching Waveforms (continued)tZZISUPPLYCL

Página 19

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 26 of 31Ordering InformationTab l e 1 lists the CY7C1471BV33, CY7C1473BV33 key packag

Página 20

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 27 of 31Package DiagramsFigure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Out

Página 21

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 28 of 31Figure 9. 165-ball FBGA (15 × 17 × 1.40 mm) (0.45 Ball Diameter) Package Out

Página 22

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 29 of 31Acronyms Document ConventionsUnits of MeasureAcronym DescriptionCENclock enab

Página 23

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 3 of 31ContentsPin Configurations ...

Página 24

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 30 of 31Document History PageDocument Title: CY7C1471BV33/CY7C1473BV33, 72-Mbit (2 M

Página 25

Document Number: 001-15029 Rev. *G Revised May 25, 2012 Page 31 of 31All products and company names mentioned in this document may be the trademarks

Página 26 - Ordering Code Definitions

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 4 of 31Pin ConfigurationsFigure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinoutCY7C1471BV3

Página 27

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 5 of 31Figure 2. 100-pin TQFP (14 × 20 × 1.4 mm) pinoutCY7C1473BV33 (4 M × 18)Pin Co

Página 28

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 6 of 31Figure 3. 165-ball FBGA (15 × 17 × 1.4 mm) pinoutPin Configurations (continue

Página 29 - Units of Measure

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 7 of 31Pin DefinitionsName I/O DescriptionA0, A1, A Input-SynchronousAddress inputs u

Página 30

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 8 of 31Functional OverviewThe CY7C1471BV33, and CY7C1473BV33 are synchronousflow thro

Página 31 - PSoC Solutions

CY7C1471BV33CY7C1473BV33Document Number: 001-15029 Rev. *G Page 9 of 31simplify read/modify/write sequences, which can be reduced tosimple byte write

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