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CY7C1354CV25

CY7C1356CV25

Document Number: 38-05537 Rev. *M Page 8 of 33

Functional Overview

The CY7C1354CV25/CY7C1356CV25 are

synchronous-pipelined burst NoBL SRAMs designed specifically

to eliminate wait states during write/read transitions. All

synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock signal is qualified with the

clock enable input signal (CEN

). If CEN is HIGH, the clock signal

is not recognized and all internal states are maintained. All

synchronous operations are qualified with CEN. All data outputs

pass through output registers controlled by the rising edge of the

clock. Maximum access delay from the clock rise (t

) is 2.8 ns

(250-MHz device).

Accesses can be initiated by asserting all three chip enables

(CE

, CE

) active at the rising edge of the clock. If clock

enable (CEN

) is active LOW and ADV/LD is asserted LOW, the

address presented to the device will be latched. The access can

either be a read or write operation, depending on the status of

the write enable (WE

). BW

[d:a]

can be used to conduct byte write

operations.

Write operations are qualified by the write enable (WE

). All writes

are simplified with on-chip synchronous self-timed write circuitry.

Three synchronous chip enables (CE

, CE

) and an

asynchronous output enable (OE

) simplify depth expansion. All

operations (reads, writes, and deselects) are pipelined. ADV/LD

should be driven LOW once the device has been deselected in

order to load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN

is asserted LOW, (2) CE

, CE

and CE

are all asserted active, (3) the write enable input signal

is deasserted HIGH, and (4) ADV/LD is asserted LOW. The

address presented to the address inputs is latched into the

address register and presented to the memory core and control

logic. The control logic determines that a read access is in

progress and allows the requested data to propagate to the input

of the output register. At the rising edge of the next clock the

requested data is allowed to propagate through the output

provided OE

is active LOW. After the first clock of the read

access the output buffers are controlled by OE

and the internal

control logic. OE

must be driven LOW in order for the device to

drive out the requested data. During the second clock, a

subsequent operation (read/write/deselect) can be initiated.

Deselecting the device is also pipelined. Therefore, when the

SRAM is deselected at clock rise by one of the chip enable

signals, its output will tri-state following the next clock rise.

Burst Read Accesses

The CY7C1354CV25/CY7C1356CV25 have an on-chip burst

counter that allows the user the ability to supply a single address

and conduct up to four reads without reasserting the address

inputs. ADV/LD

must be driven LOW in order to load a new

address into the SRAM, as described in Single Read Accesses.

The sequence of the burst counter is determined by the MODE

input signal. A LOW input on MODE selects a linear burst mode,

a HIGH selects an interleaved burst sequence. Both burst

counters use A0 and A1 in the burst sequence, and will wrap

around when incremented sufficiently. A HIGH input on ADV/LD

will increment the internal burst counter regardless of the state

of chip enables inputs or WE

. WE is latched at the beginning of

a burst cycle. Therefore, the type of access (read or write) is

maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN

is asserted LOW, (2) CE

, CE

and CE

are all asserted active, and (3) the write signal WE is

asserted LOW. The address presented to A

–A

is loaded into

the address register. The write signals are latched into the

control logic block.

On the subsequent clock rise the data lines are automatically

tri-stated regardless of the state of the OE

input signal. This

allows the external logic to present the data on DQ

and DQP

(DQ

a,b,c,d

/DQP

a,b,c,d

for CY7C1354CV25 and DQ

a,b

/DQP

a,b

for

CY7C1356CV25). In addition, the address for the subsequent

access (read/write/deselect) is latched into the address register

(provided the appropriate control signals are asserted).

Power supply Power supply inputs to the core of the device.

DDQ

I/O power

supply

Power supply for the I/O circuitry.

Ground Ground for the device. Should be connected to ground of the system.

NC – No connects. This pin is not connected to the die.

NC/18M,

NC/36M,

NC/72M,

NC/144M,

NC/288M,

NC/576M,

NC/1G

– These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M 288M,

576M, and 1G densities.

ZZ Input-

asynchronous

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with

data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an

internal pull-down.

Pin Definitions (continued)

Pin Name I/O Type Pin Description

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 32 33

CY7C1354CV25 1
CY7C1356CV25 1

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