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CY2291/CY2291F/CY2291I

CY2292/CY2292F/CY2292I

CY2295/CY2295I

Operation

The CY2291, CY2292 and CY2295 are a third-generation fam-

ily of clock generators. The CY2291 is upwardly compatible

with the industry standard ICD2023 and ICD2028 and contin-

ues their tradition by providing a high level of customizable

features to meet the diverse clock generation needs of modern

motherboards and other synchronous systems. The CY2292

differs from the CY2291 in that it comes in a 16-pin 150-mil

SOIC package, and does not provide either the 32-kHz or

CLKF outputs. The CY2295 is available in a space-saving

28-pin SSOP package.

All parts provide a highly configurable set of clocks for PC

motherboard applications. Each of the four configurable clock

outputs (CLKA–CLKD) can be assigned 1 of 30 frequencies in

any combination. Multiple outputs configured for the same or

[3]

frequencies will have low (<500 ps) skew, in effect

providing on-chip buffering for heavily loaded signals.

The CY2291, CY2292, and CY2295 can be configured for ei-

ther 5V or 3.3V operation. The internal ROM tables use

EPROM technology, allowing full customization of output fre-

quencies. The reference oscillator has been designed for

10-MHz to 25-MHz crystals, providing additional flexibility. No

external components are required with this crystal. Alterna-

tively, an external reference clock of frequency between 1 MHz

and 30 MHz can be used. Customers using the 32-kHz oscil-

lator on the CY2291 or CY2295 should connect a 10-MΩ re-

sistor in parallel with the 32-kHz crystal.

Output Configuration

The CY2291 and CY2295 (and CY2292) have five (four) inde-

pendent frequency sources on chip. These are the 32-kHz os-

cillator (not available on CY2292), the reference oscillator, and

three Phase Locked Loops (PLLs). Each PLL has a specific

function. The System PLL (SPLL) drives the CLKF output (not

available on CY2292) and provides fixed output frequencies

on the configurable outputs. The SPLL offers the most output

frequency divider options. The CPU PLL (CPLL) is controlled

by the select inputs (S0–S2) to provide eight user-selectable

frequencies with smooth slewing between frequencies. The

Utility PLL (UPLL) provides the most accurate clock. It is often

used for miscellaneous frequencies not provided by the other

frequency sources.

All configurations are EPROM programmable, providing short

sample and production lead times. Please refer to the applica-

tion note “Understanding the CY2291, CY2292, and CY2295”

for information on configuring the part.

Power Saving Features

The SHUTDOWN/OE input three-states the outputs when

pulled LOW (the 32-kHz clock output is not affected). If system

shutdown is enabled (the default), a LOW on this pin also shuts

off the PLLs, counters, the reference oscillator, and all other

active components. The resulting current on the V

pins will

be less than 50 µA (for Commercial Temp. or 100 µA for Indus-

trial Temp.) plus 15 µA max. for the 32-kHz subsystem and is

typically 10 µA. After leaving shutdown mode, the PLLs will

have to re-lock. All outputs except 32K have a weak pull-down

so that the outputs do not float when three-stated.

[4]

The S2/SUSPEND input can be configured to shut down a

customizable set of outputs and/or PLLs, when LOW. All PLLs

and any of the outputs except 32K can be shut off in nearly any

combination. The only limitation is that if a PLL is shut off, all

outputs derived from it must also be shut off. Suspending a

PLL shuts off all associated logic, while suspending an output

simply forces a three-state condition.

[3]

The CPUCLK can slew (transition) smoothly between 8 MHz

and the maximum output frequency (100 MHz at 5V/80 MHz

at 3.3V for Commercial Temp. parts or 90 MHz at 5V/66.6 MHz

at 3.3V for Industrial Temp. and for field-programmed parts).

This feature is extremely useful in “Green” PC and laptop ap-

plications, where reducing the frequency of operation can re-

sult in considerable power savings. This feature meets all 486

and Pentium processor slewing requirements.

CyClocks™ Software

CyClocks is an easy-to-use application that allows you to con-

figure any one of the EPROM programmable clocks offered by

Cypress. You may specify the input frequency, PLL & output

frequencies, and different functional options. Please note the

output frequency ranges in this datasheet when specifying

them in CyClocks to ensure that you stay within the limits.

CyClocks also has a power calculation feature that allows you

to see the power consumption of your specific configuration.

You can download a copy of CyClocks for free on Cypress’s

website at www.cypress.com.

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