Cypress Semiconductor STK14C88-5 Manual do Utilizador descarregar pdf (Página 8)

STK14C88

Document Number: 001-52038 Rev. *D Page 8 of 21

Hardware Mode Selection

E W HSB A

- A

(hex) Mode I/O Power Notes

H X H X Not Selected Output High Z Standby –

L H H X Read SRAM Output Data Active 23

L L H X Write SRAM Input Data Active –

X X L X Nonvolatile STORE Output High Z l

Hardware STORE Cycle

No.

Symbols

Parameter

STK14C88

Units Notes

Standard Alternate Min Max

22 t

STORE

HLHZ

STORE cycle duration – 10 ms 17

23 t

DELAY

HLQZ

Time allowed to complete SRAM cycle 1 – s17

24 t

RECOVER

HHQX

Hardware STORE High to inhibit Off – 700 ns 17, 18

25 t

HLHX

Hardware STORE pulse width 15 – ns –

26 t

HLBL

Hardware STORE Low to STORE busy – 300 ns –

Figure 8. Hardware STORE Cycle

DATA VALID

HSB (IN)

DATA VALID

HLHX

DELAY

STORE

RECOVER

HIGH IMPEDANCE

HLBL

HIGH IMPEDANCE

DQ (DATA OUT)

HSB (OUT)

Notes

16. HSB

STORE operation occurs only if an SRAM write is done since the last nonvolatile cycle. After the STORE (if any) completes, the part goes into standby mode,

inhibiting all operations until HSB rises

17. E

and G low, W high for output behavior.

18. t

RECOVER

is only applicable after t

STORE

is complete.

Not Recommended for New Designs

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