Cypress Semiconductor STK14C88-5 Manual do Utilizador descarregar pdf (Página 6)

STK14C88

Document Number: 001-52038 Rev. *D Page 6 of 21

Figure 5. SRAM Read Cycle 2: E and G Controlled

[6]

SRAM Read Cycles #1 and #2

= 5.0 V ± 10%)

[9]

NO.

Symbols

Parameter

STK14C88-25 STK14C88-35 STK14C88-45

Unit

Min Max Min Max Min Max#1, #2 Alt.

ELQV

ACS

Chip enable access time – 25 – 35 – 45 ns

AVAV

[6]

ELEH

[6]

Read cycle time 25 35 – 45 – ns

AVQV

Address access time – 25 – 35 – 45 ns

GLQV

Output enable to data valid – 10 – 15 – 20 ns

AXQX

[7]

Output hold after address change 5 – 5 – 5 – ns

ELQX

Address change or chip enable to

output active

5–5–5–ns

EHQZ

[8]

Address change or chip disable to

output inactive

–10–13–15ns

GLQX

OLZ

Output enable to output active 0 – 0 – 0 – ns

GHQZ

[8]

OHZ

Output disable to output inactive – 10 – 13 15 ns

10 t

ELICCH

[10]

Chip enable to power active 0 – 0 0 – ns

11 t

EHICCL

[10]

Chip disable to power standby – 25 35 – 45 ns

Figure 4. SRAM Read Cycle 1: Address Controlled

[6, 7]

Notes

6. W

and HSB must be high during SRAM read cycles.

7. I/O state assumes E

and G < V

and W  V

; device is continuously selected.

8. Measured ± 200 mV from steady state output voltage.

9. V

reference levels throughout this datasheet refer to V

if that is where the power supply connection is made, or V

CAP

if V

is connected to ground.

10. These

parameters are guaranteed but not tested.

DATA VALID

AXQX

AVQV

DQ (DATA OUT)

ADDRESS

AVAV

Not Recommended for New Designs

1 2 3 4 5 6 7 8 9 10 11 ... 21 22

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