Cypress Semiconductor STK14C88-5 Manual do Utilizador descarregar pdf (Página 7)

STK14C88

Document Number: 001-52038 Rev. *D Page 7 of 21

SRAM Write Cycle #1 and #2

= 5.0 V ± 10%)

[15]

NO.

Symbols

Parameter

STK14C88-25 STK14C88-35 STK14C88-45

Unit

Min Max Min Max Min Max#1 #2 Alt.

12 t

AVAV

Write cycle time 25 – 35 – 45 – ns

13 t

WLWH

WLEH

Write pulse width 20 – 25 – 30 – ns

14 t

ELWH

ELEH

Chip enable to end of write 20 – 25 – 30 – ns

15 t

DVWH

DVEH

Data setup to end of write 10 – 12 – 15 – ns

16 t

WHDX

EHDX

Data hold after end of write 0 – 0 – 0 – ns

17 t

AVWH

AVEH

Address setup to end of write 20 – 25 – 30 – ns

18 t

AVWL

AVEL

Address setup to start of write 0 – 0 – 0 – ns

19 t

WHAX

EHAX

Address hold after end of write 0 – 0 – 0 – ns

20 t

WLQZ

[11, 12]

Write enable to output disable – 10 – 13 – 15 ns

21 t

WHQX

Output active after end of write 5 – 5 – 5 – ns

Figure 6. SRAM Write Cycle 1: W Controlled

[13, 14]

Figure 7. SRAM Write Cycle 2: E Controlled

[13, 14]

DATA OUT

ADDRESS

DATA IN

PREVIOUS DATA

AVAV

WHDX

WHAX

WLWH

AVWL

AVWH

DATA VALID

WLQZ

DVWH

HIGH IMPEDANCE

WHQX

ELWH

AVAV

EHDX

WLEH

EHAX

AVEL

AVEH

DATA VALID

DVEH

HIGH IMPEDANCE

ELEH

DATA OUT

ADDRESS

DATA IN

Notes

11. Measured ± 200 mV from steady state output voltage.

12. If W

is low when E goes low, the outputs remain in the high impedance state.

13. E

or W must be  V

during address transitions.

14. HSB

must be high during SRAM write cycles.

15. V

reference levels throughout this datasheet refer to V

if that is where the power supply connection is made, or V

CAP

if V

is connected to ground.

Not Recommended for New Designs

1 2 3 4 5 6 7 8 9 10 11 12 ... 21 22

Comentários a estes Manuais

Sem comentários

Cypress Semiconductor STK14C88-5 Manual do Utilizador Página 7

Comentários a estes Manuais

Manuais e produtos relacionados com não Cypress Semiconductor STK14C88-5