
Document Number: 001-52038 Rev. *D Page 13 of 21
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■ The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The
end product’s firmware should not assume an NV array is in a
set programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on, should always program a unique
NV pattern (for example, complex 4-byte pattern of 46 E6 49
53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■ Power-up boot firmware routines should rewrite the nvSRAM
into the desired state (such as autostore enabled). While the
nvSRAM is shipped in a preset state, best practice is to again
rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently (program
bugs, incoming inspection routines, and so on).
■ The V
CAP
value specified in this datasheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the max V
CAP
value because the
nvSRAM internal algorithm calculates V
CAP
charge time based
on this max V
CAP
value. Customers who want to use a larger
V
CAP
value to make sure there is extra store charge and store
time should discuss their V
CAP
size selection with Cypress to
understand any impact on the V
CAP
voltage level at the end of
a t
RECALL
period.
Preventing STORES
The STORE function can be disabled on the fly by holding HSB
high with a driver capable of sourcing 30 mA at a V
OH
of at least
2.2 V, because it must overpower the internal pull down device
that drives HSB
low for 20 ms at the onset of a STORE. When
the STK14C88 is connected for AutoStore operation (system
V
CC
connected to V
CC
and a 68 uF capacitor on V
CAP
) and V
CC
crosses V
SWITCH
on the way down, the STK14C88 attempts to
pull HSB
low; if HSB does not actually get below V
IL
, the part
stops trying to pull HSB
low and abort the STORE attempt.
Hardware Protect
The STK14C88 offers hardware protection against inadvertent
STORE operation and SRAM writes during low-voltage condi-
tions. When V
CAP
< V
SWITCH
, all externally initiated STORE
operations and SRAM writes are inhibited.
AutoStore can be completely disabled by tying V
CC
to ground
and applying + 5 V to V
CAP
. This is the AutoStore Inhibit mode;
in this mode STOREs are only initiated by explicit request using
either the software sequence or the HSB
pin.
Low Average Active Power
The STK14C88 draws significantly less current when it is cycled
at times longer than 50 ns. Figure 13 shows the relationship
between I
CC
and read cycle time. Worst case current
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, V
CC
= 5.5 V, 100% duty cycle
on chip enable). Figure 14 shows the same relationship for write
cycles. If the chip enable duty cycle is less than 100%, only
standby current is drawn when the chip is disabled. The overall
average current drawn by the STK14C88 depends on the
following items:
■ CMOS versus TTL input levels
■ The duty cycle of chip enable
■ The overall cycle rate for accesses
■ The ratio of reads to writes
■ The operating temperature
■ The V
CC
level
■ I/O loading.
Figure 13. Icc (max) Reads
Figure 14. Icc (max) Writes
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
Average Active Current (mA)
Not Recommended for New Designs
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