Cypress Semiconductor CY8C21234 Manual do Utilizador descarregar pdf (Página 34)

CY8C21634/CY8C21534

CY8C21434/CY8C21334/CY8C21234

Document Number: 38-12025 Rev. *Q Page 34 of 45

Figure 19. Definition for Timing for Fast/Standard Mode on the I

C Bus

Table 37. 2.7V AC Characteristics of the I

C SDA and SCL Pins (Fast Mode not Supported)

Symbol Description

Standard Mode Fast Mode

Units

Min Max Min Max

SCLI2C

SCL Clock Frequency 0 100 ––kHz

HDSTAI2C

Hold Time (repeated) START Condition.

After this period, the first clock pulse is

generated.

4.0 – – – μs

LOWI2C

LOW Period of the SCL Clock 4.7 – – – μs

HIGHI2C

HIGH Period of the SCL Clock 4.0 – – – μs

SUSTAI2C

Set up Time for a Repeated START

Condition

4.7 – – – μs

HDDATI2C

Data Hold Time 0 – – – μs

SUDATI2C

Data Set-up Time 250 – – –ns

SUSTOI2C

Set up Time for STOP Condition 4.0 – – – μs

BUFI2C

Bus Free Time Between a STOP and START

Condition

4.7 ––– μs

SPI2C

Pulse Width of spikes are suppressed by the

input filter.

– –––ns

SDA

SCL

Sr SP

BUFI2C

SPI2C

HDSTAI2C

SUSTOI2C

SUSTAI2C

LOWI2C

HIGHI2C

HDDATI2C

HDSTAI2C

SUDATI2C

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