Cypress Semiconductor Perform STK12C68 Manual do Utilizador

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STK12C68
64 Kbit (8 K x 8) AutoStore nvSRAM
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-51027 Rev. *G Revised March 21, 2014
Features
25 ns, 35 ns, and 45 ns access times
Hands off automatic STORE on power-down with external
68 µF capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, hardware, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
Unlimited read, write, and recall cycles
1,000,000 STORE cycles to QuantumTrap
100 year data retention to QuantumTrap
Single 5 V + 10% operation
Commercial and industrial temperatures
28-pin (330 mil) SOIC, 28-pin (300 mil) PDIP, 28-pin (600 mil)
PDIP packages
28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages
RoHS compliance
Functional Description
The Cypress STK12C68 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB
pin.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
128 X 512
Quantum Trap
128 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
0
-
A
12
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
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Página 1 - STK12C68

STK12C6864 Kbit (8 K x 8) AutoStore nvSRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document Numb

Página 2

STK12C68Document Number: 001-51027 Rev. *G Page 10 of 22AC Switching Characteristics SRAM Read CycleParameterDescription25 ns 35 ns 45 ns UnitMin M

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STK12C68Document Number: 001-51027 Rev. *G Page 11 of 22SRAM Write CycleParameterDescription25 ns 35 ns 45 ns UnitMin Max Min Max Min MaxCypressPar

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STK12C68Document Number: 001-51027 Rev. *G Page 12 of 22AutoStore or Power-up RECALLParameter Alt DescriptionSTK12C68UnitMin MaxtHRECALL [13]tRESTORE

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STK12C68Document Number: 001-51027 Rev. *G Page 13 of 22Software Controlled STORE/RECALL CycleThe software controlled STORE/RECALL cycle follows. [18

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STK12C68Document Number: 001-51027 Rev. *G Page 14 of 22Hardware STORE CycleParameter Alt DescriptionSTK12C68UnitMin MaxtSTORE [9, 14]tHLHZ STORE Cyc

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STK12C68Document Number: 001-51027 Rev. *G Page 15 of 22Part Numbering NomenclaturePackaging Option:TR = Tape and ReelBlank = TubeSpeed:25 - 25 ns35

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STK12C68Document Number: 001-51027 Rev. *G Page 16 of 22Package DiagramsFigure 14. 28-Pin (330 Mil) SOIC (51-85058)51-85058 *C

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STK12C68Document Number: 001-51027 Rev. *G Page 17 of 22Figure 15. 28-Pin (300 Mil) PDIP (51-85014)Package Diagrams (continued)51-85014 *G

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STK12C68Document Number: 001-51027 Rev. *G Page 18 of 22Figure 16. 28-Pin (600 Mil) PDIP (51-85017)Package Diagrams (continued)51-85017 *E

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STK12C68Document Number: 001-51027 Rev. *G Page 19 of 22Figure 17. 28-Pin (300 Mil) Side Braze DIL (001-51695)Package Diagrams (continued)001-51695

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STK12C68Document Number: 001-51027 Rev. *G Page 2 of 22ContentsPin Configurations ... 3Pin De

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STK12C68Document Number: 001-51027 Rev. *G Page 20 of 22Figure 18. 28-Pad (350 Mil) LCC (001-51696)Package Diagrams (continued)001-51696 *B

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STK12C68Document Number: 001-51027 Rev. *G Page 21 of 22Document History PageDocument Title: STK12C68 64 Kbit (8 K x 8) AutoStore nvSRAMDocument Numb

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Document Number: 001-51027 Rev. *G Revised March 21, 2014 Page 22 of 22All products and company names mentioned in this document may be the trademark

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STK12C68Document Number: 001-51027 Rev. *G Page 3 of 22 Pin ConfigurationsPin DefinitionsPin Name Alt I/O Type DescriptionA0–A12Input Address Inputs

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STK12C68Document Number: 001-51027 Rev. *G Page 4 of 22Device OperationThe STK12C68 nvSRAM is made up of two functionalcomponents paired in the same

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STK12C68Document Number: 001-51027 Rev. *G Page 5 of 22Figure 3. AutoStore Inhibit ModeIf the power supply drops faster than 20 us/volt before Vccre

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STK12C68Document Number: 001-51027 Rev. *G Page 6 of 22Software RECALLData is transferred from the nonvolatile memory to the SRAM bya software addres

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STK12C68Document Number: 001-51027 Rev. *G Page 7 of 22Best PracticesnvSRAM products have been used effectively for over 15 years.While ease-of-use i

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STK12C68Document Number: 001-51027 Rev. *G Page 8 of 22Maximum RatingsExceeding maximum ratings may shorten the useful life of the device. These user

Página 22 - PSoC Solutions

STK12C68Document Number: 001-51027 Rev. *G Page 9 of 22Data Retention and EnduranceParameter Description Min UnitDATARData retention 100 YearsNVCNonv

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