Cypress Semiconductor CY8C21234 Manual do Utilizador descarregar pdf (Página 32)

CY8C21634/CY8C21534

CY8C21434/CY8C21334/CY8C21234

Document Number: 38-12025 Rev. *Q Page 32 of 45

Table 33. 3.3V AC External Clock Specifications

Symbol Description Min Typ Max Units Notes

OSCEXT

Frequency with CPU Clock divide by 1 0.093 – 12.3 MHz Maximum CPU frequency is 12

MHz at 3.3V. With the CPU clock

divider set to 1, the external clock

must adhere to the maximum

frequency and duty cycle

requirements.

OSCEXT

Frequency with CPU Clock divide by 2 or

greater

0.186 – 24.6 MHz If the frequency of the external clock

is greater than 12 MHz, the CPU

clock divider must be set to 2 or

greater. In this case, the CPU clock

divider ensures that the fifty percent

duty cycle requirement is met.

– High Period with CPU Clock divide by 1 41.7

– 5300 ns

– Low Period with CPU Clock divide by 1 41.7

– –ns

– Power Up IMO to Switch 150

– – μs

Table 34. 2.7V AC External Clock Specifications

Symbol Description Min Typ Max Units Notes

OSCEXT

Frequency with CPU Clock divide by 1 0.093 –3.08

MHz Maximum CPU frequency is 3 MHz

at 2.7V. With the CPU clock divider

set to 1, the external clock must

adhere to the maximum frequency

and duty cycle requirements.

OSCEXT

Frequency with CPU Clock divide by 2 or

greater

0.186 – 6.35 MHz If the frequency of the external clock

is greater than 3 MHz, the CPU

clock divider must be set to 2 or

greater. In this case, the CPU clock

divider ensures that the fifty percent

duty cycle requirement is met.

– High Period with CPU Clock divide by 1 160

– 5300 ns

– Low Period with CPU Clock divide by 1 160 – –ns

– Power Up IMO to Switch 150

– – μs

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