Cypress Semiconductor enCoRe CY7C601xx Guia do Utilizador descarregar pdf (Página 57)

CY7C601xx

CY7C602xx

Document 38-16016 Rev. *C Page 57 of 62

Figure 22. SPI Master Timing, CPHA = 0

Figure 23. SPI Slave Timing, CPHA = 0

MSB

T

MSU

LSB

T

MHD

T

SCKH

T

MDO1

SS

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

MISO

(SS is under firmware control in SPI Master mode)

T

SCKL

T

MDO

LSBMSB

MSB

T

SSU

LSB

T

SHD

T

SCKH

T

SDO1

SS

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

MISO

T

SCKL

T

SDO

LSBMSB

T

SSS

T

SSH

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