Cypress Semiconductor enCoRe CY7C601xx Guia do Utilizador descarregar pdf (Página 41)

CY7C601xx

CY7C602xx

Document 38-16016 Rev. *C Page 41 of 62

SPI Data Register

When an interrupt occurs to indicate to firmware that an byte of receive data is available, or the transmitter holding register is

empty, firmware has 7 SPI clocks to manage the buffers—to empty the receiver buffer, or to refill the transmit holding register.

Failure to meet this timing requirement will result in incorrect data transfer.

SPI Configure Register

Table 63.SPI Data Register (SPIDATA) [0x3C] [R/W]

Bit # 7 6 5 4 3 2 1 0

Field SPIData[7:0]

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 000 0

When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register.

Bit [7:0]: SPI Data [7:0]

Table 64.SPI Configure Register (SPICR) [0x3D] [R/W]

Bit # 7 6 5 4 3 2 1 0

Field Swap LSB First Comm Mode CPOL CPHA SCLK Select

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 000 0

Bit 7: Swap

0 = Swap function disabled

1 = The SPI block swaps its use of SMOSI and SMISO. Among other things, this can be useful in implementing single wire SPI-

like communications.

Bit 6: LSB First

0 = The SPI transmits and receives the MSB (Most Significant Bit) first

1 = The SPI transmits and receives the LSB (Least Significant Bit) first.

Bit [5:4]: Comm Mode [1:0]

0 0: All SPI communication disabled

0 1: SPI master mode

1 0: SPI slave mode

1 1: Reserved

Bit 3: CPOL

This bit controls the SPI clock (SCLK) idle polarity.

0 = SCLK idles low

1 = SCLK idles high

Bit 2: CPHA

The Clock Phase bit controls the phase of the clock on which data is sampled. Table 65 below shows the timing for the various

combinations of LSB First, CPOL, and CPHA.

Bit [1:0]: SCLK Select

This field selects the speed of the master SCLK. When in master mode, SCLK is generated by dividing the base CPUCLK

Important Note for Comm Modes 01b or 10b (SPI Master or SPI Slave):

When configured for SPI, (SPI Use = 1 – Table 58), the input/output direction of pins P1.3, P1.5, and P1.6 is set automatically

by the SPI logic. However, pin P1.4's input/output direction is NOT automatically set; it must be explicitly set by firmware. For

SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4 must be configured as an input.

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