Cypress Semiconductor enCoRe CY7C601xx Guia do Utilizador descarregar pdf (Página 48)

CY7C601xx

CY7C602xx

Document 38-16016 Rev. *C Page 48 of 62

Figure 15. 16-bit Free Running Counter Loading Timing Diagram

Figure 16. Memory Mapped Registers Read/Write Timing Diagram

clk_sys

write

valid

addr

write data

FRT reload

ready

Clk Timer

12b Prog Timer

12b reload

interrupt

Capture timer

clk

16b free running

counter load

16b free

running counter

00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0

16-bit free running counter loading timing

12-bit programmable timer load timing

Memory mapped registers Read/Write timing diagram

clk_sys

rd_wrn

Valid

Addr

rdata

wdata

1 2 ... 43 44 45 46 47 48 49 50 51 52 53 ... 61 62

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Cypress Semiconductor enCoRe CY7C601xx Guia do Utilizador Página 48